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TPS26633RGER

Texas Instruments · Supervisor And Reset ICs · VQFN-24-EP(4x4)

TPS26633RGER from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN power_in Power input that connects to the DRAIN of the internal FET.
2 IN power_in Power input that connects to the DRAIN of the internal FET.
3 B_GATE output Blocking FET gate driver output; connect to the GATE of the external N-FET, and leave floating if the external FET is not used.
4 DRV output Blocking FET fast pulldown switch drive; connect to the GATE of the external pulldown switch, and leave floating if the external N-FET is not used.
5 IN_SYS power_in Power input and supply voltage of the device; connect to the source of the blocking FET when used, or short to IN if no blocking FET is used.
6 UVLO input Input for setting the programmable undervoltage lockout threshold; an undervoltage event turns off the internal FET and asserts FLT, and connecting UVLO to GND selects the internal default threshold.
7 PLIM input Input for setting the programmable output power limiting threshold; connect a resistor across PLIM to GND to set the output power limit, or connect PLIM to GND if the PLIM feature is not used.
8 GND power_in Connect GND to system ground.
9 dVdT bidirectional A capacitor from this pin to GND sets the output voltage slew rate.
10 ILIM bidirectional A resistor from this pin to GND sets the overload and short-circuit current limit.
11 MODE input Mode selection pin for the overload fault response.
12 SHDN input Shutdown pin; pulling SHDN low puts the device into low-power shutdown mode, and cycling SHDN resets a device latched off by a fault.
13 IMON output Analog current monitor output that sources a scaled-down ratio of the current through the internal FET; a resistor from this pin to GND converts it to voltage, and it can be left floating if unused.
14 FLT output Open-drain fault event indicator; leave floating or connect to GND if unused.
15 PGTH input PGOOD comparator input.
16 PGOOD output Active-high power-good output that goes high when PGTH crosses the V(PGTHR) threshold and the internal FET is enhanced; connect to GND or leave floating if unused.
17 OUT power_out Power output of the device.
18 OUT power_out Power output of the device.
19 N.C unconnected No connect.
20 N.C unconnected No connect.
21 N.C unconnected No connect.
22 N.C unconnected No connect.
23 N.C unconnected No connect.
24 N.C unconnected No connect.
25 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-24-EP(4x4)
Category Power Management (PMIC)
Pins 25

CAD (KiCad official)

  • Symbol: TPS26633RGER
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: tps26633rger-etched.step / tps26633rger-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps26633rger.step / tps26633rger.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (60 pp, sha256 63ce6e9453e4499b, retrieved 2026-10-10, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF