component
TPS259823ONRGER
Public Made by Adomby adom
Texas Instruments Surge Protection Devices (SPDs), QFN-24(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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TPS259823ONRGER
Texas Instruments · Surge Protection Devices (SPDs) · QFN-24(4x4)
TPS259823ONRGER from Texas Instruments, in a QFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | power_in | Power input to the eFuse, operating range 2.7 V to 24 V with an absolute maximum of 30 V. |
| 2 | IN | power_in | Power input to the eFuse, operating range 2.7 V to 24 V with an absolute maximum of 30 V. |
| 3 | IN | power_in | Power input to the eFuse, operating range 2.7 V to 24 V with an absolute maximum of 30 V. |
| 4 | GND | power_in | Connect to system ground; the reference for all internal signals. |
| 5 | GND | power_in | Connect to system ground; the reference for all internal signals. |
| 6 | EN/UVLO | input | Active-high enable with adjustable UVLO set by a resistor divider from IN to GND; the pin must not be left floating and has an absolute maximum of 7 V. |
| 7 | ITIMER | output | A capacitor to GND sets the overcurrent blanking interval; leave open for the fastest response, and shorting it to GND is detected as a fault that turns the device off. |
| 8 | ILIM | output | A resistor to GND sets the output current-limit and fast-trip thresholds; the pin must not be left floating, and an open pin sets the limit to zero. |
| 9 | IMON | output | Analog load-current monitor that sources a current proportional to load current (246 µA/A typical), converted to a voltage by a resistor to GND. |
| 10 | RETRY_DLY | output | A capacitor to GND sets the delay before the device attempts an automatic restart after a fault; tying the pin to GND selects latch-off with no retry. |
| 11 | NRETRY | output | A capacitor to GND sets the number of automatic restart attempts after a fault; tying the pin to GND selects unlimited retries. |
| 12 | LDSTRT | input | Load detect/handshake input; a capacitor to GND sets the window in which the load must pull this pin low after PG asserts, tie to GND if unused, and the pin must not be left floating. |
| 13 | PG | output | Active-high open-drain power-good output that requires an external pull-up, asserts when the FET is fully enhanced and output is at its maximum, and stays low when VIN is below VUVP; absolute maximum 7 V. |
| 14 | GND | power_in | Connect to system ground; the reference for all internal signals. |
| 15 | dVdt | input | A capacitor to GND sets the output turn-on slew rate; leave open for the fastest ramp during start-up, with a capacitor voltage rating of VIN + 4 V. |
| 16 | IN | power_in | Power input to the eFuse, operating range 2.7 V to 24 V with an absolute maximum of 30 V. |
| 17 | OUT | power_out | Switched power output to the load from the internal FET; absolute range is -0.8 V to the lesser of 30 V or VIN + 0.3 V. |
| 18 | OUT | power_out | Switched power output to the load from the internal FET; absolute range is -0.8 V to the lesser of 30 V or VIN + 0.3 V. |
| 19 | OUT | power_out | Switched power output to the load from the internal FET; absolute range is -0.8 V to the lesser of 30 V or VIN + 0.3 V. |
| 20 | OUT | power_out | Switched power output to the load from the internal FET; absolute range is -0.8 V to the lesser of 30 V or VIN + 0.3 V. |
| 21 | OUT | power_out | Switched power output to the load from the internal FET; absolute range is -0.8 V to the lesser of 30 V or VIN + 0.3 V. |
| 22 | OUT | power_out | Switched power output to the load from the internal FET; absolute range is -0.8 V to the lesser of 30 V or VIN + 0.3 V. |
| 23 | OUT | power_out | Switched power output to the load from the internal FET; absolute range is -0.8 V to the lesser of 30 V or VIN + 0.3 V. |
| 24 | OUT | power_out | Switched power output to the load from the internal FET; absolute range is -0.8 V to the lesser of 30 V or VIN + 0.3 V. |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | QFN-24(4x4) |
| Category | Circuit Protection |
| Pins | 25 |
CAD (KiCad official)
- Symbol:
TPS259823ONRGER - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm - 3D model: QFN-24(4x4) (KiCad packages3D, STEP)
- 3D model files:
tps259823onrger-etched.step/tps259823onrger-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps259823onrger.step/tps259823onrger.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (55 pp, sha256
f4a0f06cfbd81f26, retrieved 2026-10-08, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).