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TPS259807ONRGER

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Texas Instruments Surge Suppressors, VQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TPS259807ONRGER

Texas Instruments · Surge Suppressors · VQFN-24-EP(4x4)

TPS259807ONRGER from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN power_in Power input; the IN pins and the exposed Pad 1 carry the input supply (2.7 V to 24 V operating, 30 V absolute maximum).
2 IN power_in Power input; the IN pins and the exposed Pad 1 carry the input supply (2.7 V to 24 V operating, 30 V absolute maximum).
3 IN power_in Power input; the IN pins and the exposed Pad 1 carry the input supply (2.7 V to 24 V operating, 30 V absolute maximum).
16 IN power_in Power input; the IN pins and the exposed Pad 1 carry the input supply (2.7 V to 24 V operating, 30 V absolute maximum).
4 GND power_in Connect to system ground.
5 GND power_in Connect to system ground.
14 GND power_in Connect to system ground.
6 EN/UVLO input Active-high enable; a resistor divider from the input supply to GND adjusts the undervoltage lockout threshold, absolute maximum 7 V, do not leave floating.
7 ITIMER passive A capacitor to GND sets the overcurrent blanking interval before the overcurrent response acts; leave open for fastest response, shorting to GND is detected as a fault.
8 ILIM passive An external resistor to GND sets the output current limit and fast-trip thresholds (fast trip = 2.1 x ILIM); do not leave floating.
9 IMON output Analog load current monitor that sources a current proportional to load current, converted to voltage by a resistor to GND.
10 RETRY_DLY passive A capacitor to GND sets the delay after a fault shutdown before automatic restart; connect to GND for latch-off operation.
11 NRETRY passive A capacitor to GND sets the number of automatic restart attempts after a fault shutdown; connect to GND for indefinite retries.
12 LDSTRT input Load detect/handshake input; a capacitor to GND sets the time after PG assertion within which the pin must be pulled low, absolute maximum 7 V, connect to GND if unused, do not leave floating.
13 PG output Active-high open-drain power good indication needing an external pull-up, asserted when the FET is fully enhanced and output has reached maximum voltage, absolute maximum 7 V.
15 dVdt passive A capacitor to GND sets the output turn-on slew rate; leave floating for the fastest start-up slew rate.
17 OUT power_out Power output.
18 OUT power_out Power output.
19 OUT power_out Power output.
20 OUT power_out Power output.
21 OUT power_out Power output.
22 OUT power_out Power output.
23 OUT power_out Power output.
24 OUT power_out Power output.
25 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-24-EP(4x4)
Category TVS/Fuse/Board Level Protection
Pins 25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Maximum Input Voltage Range VIN -0.3 30 V IN pin 6
Maximum Output Voltage Range (min only; max is min(30V, VIN+0.3)) VOUT -0.8 V OUT pin 6
Maximum Enable Pin Voltage Range VEN/UVLO -0.3 7 V EN/UVLO pin 6
Maximum LDSTRT Pin Voltage Range VLDSTRT 7 V LDSTRT pin 6
Maximum PG Pin Voltage Range VPG -0.3 7 V PG pin 6
Maximum Soldering Temperature TLEAD 300 °C 6
Storage temperature Tstg -65 150 °C 6
ESD HBM V(ESD) -2000 2000 V ANSI/ESDA/JEDEC JS-001, all pins 6
ESD CDM V(ESD) -1000 1000 V JESD22-C101, all pins 6
Input Voltage Range VIN 2.7 24 V IN pin 7
Enable Pin Voltage Range VEN/UVLO 6 V EN/UVLO pin 7
LDSTRT Pin Capacitor Voltage Rating VLDSTRT 4 V LDSTRT pin 7
PG Pin Voltage Range VPG 6 V PG pin 7
ITIMER Pin Capacitor Voltage Rating VITIMER 4 V ITIMER pin 7
NRETRY Pin Capacitor Voltage Rating VNRETRY 4 V NRETRY pin 7
RETRY_DLY Pin Capacitor Voltage Rating VRETRY_DLY 4 V RETRY_DLY pin 7
ILIM Pin Resistor RILIM 182 1650 Ω ILIM pin 7
Continuous Switch Current IMAX 8 A IN to OUT 7
Junction temperature TJ -40 125 °C 7
IN Quiescent Current IQ 800 1200 µA VEN ≥ VUVLO(R) 8
IN Shutdown Current ISD 204 300 µA VSD < VEN < VUVLO 8
IN Shutdown Current ISD 3.67 20 µA VEN < VSD 8
IN Undervoltage Protection Threshold, rising VUVP 2.46 2.53 2.6 V VIN Rising 8
IN Undervoltage Protection Threshold, falling VUVP 2.35 2.42 2.49 V VIN Falling 8
Current Monitor Gain (IIMON:IOUT) GIMON 228.78 246 263.22 µA/A 3 A ≤ IOUT ≤ min(8 A, ILIM) 8
Current Limit Threshold ILIM 1.76 2 2.17 A RILIM = 773 Ω, TJ = 25 ℃ 8
Current Limit Threshold ILIM 1.53 2 2.43 A RILIM = 773 Ω, TJ = -40 to 125 ℃ 8
Current Limit Threshold ILIM 4.75 4.98 5.23 A RILIM = 300 Ω, TJ = 25 ℃ 8
Current Limit Threshold ILIM 4.36 4.98 5.66 A RILIM = 300 Ω, TJ = -40 to 125 ℃ 8
Current Limit Threshold ILIM 7.77 8.13 8.54 A RILIM = 182 Ω, TJ = 25 ℃ 8
Current Limit Threshold ILIM 7.23 8.13 9.07 A RILIM = 182 Ω, TJ = -40 to 125 ℃ 8
EN/UVLO Pin Voltage Threshold, rising VUVLO(R) 1.18 1.2 1.23 V VEN Rising 8
EN/UVLO Pin Voltage Threshold, falling VUVLO(F) 1.08 1.1 1.13 V VEN Falling 8
EN/UVLO Threshold for Lowest Shutdown Current VSD 0.59 0.8 V VEN Falling 8
ON State Resistance RON 3 mΩ TJ = 25 ℃, IOUT = 2 A 8
ON State Resistance RON 5 mΩ TJ = -40 to 125 ℃, IOUT = 2 A 8
EN/UVLO Pin Leakage Current IENLKG 0.1 µA 8
PG Pin Low Voltage VPGD 651 786 mV VIN < VUVP, VEN < VSD, IPG = 26 µA 8
PG Pin Low Voltage VPGD 320 mV VIN = 3.3V, IPG ≤ 5 mA 8
PG Pin Low Voltage VPGD 100 mV VIN ≥ 5V, IPG ≤ 5 mA 8
PG Pin Leakage Current (PG asserted) IPGLKG 1.7 µA PG pulled up to 5 V through 10 kΩ 8
VIN - VOUT Threshold when PG is de-asserted VPGTHD 0.224 0.326 0.45 V 9
RETRY_DLY Oscillator Hysteresis VRETRY_DLY_HYS 0.65 0.75 0.85 V 9
RETRY_DLY Pin Bias Current IRETRY_DLY 1.7 2.05 2.5 µA 9
NRETRY Oscillator Hysteresis VNRETRY_HYS 0.65 0.75 0.85 V 9
NRETRY Pin Bias Current INRETRY 1.7 2.05 2.5 µA 9
ITIMER Discharge Current IITIMER 1.4 2.1 2.8 µA ISC > IOUT > ILIM 9
ITIMER Comparator Voltage Threshold Delta ΔVITIMER 0.7 0.98 1.3 V ISC > IOUT > ILIM, ITIMER Voltage Falling 9
LDSTRT Rising Threshold VLDSTRT 1.1 1.21 1.3 V LDSTRT voltage rising 9
LDSTRT Charging Current ILDSTRT 1.7 2.05 2.4 µA PG asserted 9
dVdt Pin Charging Current IdVdt 2 4.6 6.33 µA 9
Junction-to-ambient thermal resistance RθJA 34.6 °C/W RGE (QFN) 24 pins 7
Junction-to-case (top) thermal resistance RθJC(top) 36.7 °C/W RGE (QFN) 24 pins 7
Junction-to-board thermal resistance RθJB 11.2 °C/W RGE (QFN) 24 pins 7
Junction-to-case (bottom) thermal resistance RθJC(bot) 1.6 °C/W RGE (QFN) 24 pins 7

CAD (KiCad official)

  • Symbol: TPS259807ONRGER
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: tps259807onrger-etched.step / tps259807onrger-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps259807onrger.step / tps259807onrger.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (52 pp, sha256 b72f89671f163ccc, retrieved 2026-10-23, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF