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TPS25832AQWRHBRQ1

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Texas Instruments Power Management - Specialized, QFN-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TPS25832AQWRHBRQ1

Texas Instruments · Power Management - Specialized · QFN-32(5x5)

TPS25832AQWRHBRQ1 from Texas Instruments, in a QFN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN power_in Input supply to the regulator; connect high-quality bypass capacitor(s) directly to this pin and PGND, with IN to PGND limited to -0.3 V to 40 V.
2 IN power_in Input supply to the regulator; connect high-quality bypass capacitor(s) directly to this pin and PGND, with IN to PGND limited to -0.3 V to 40 V.
3 IN power_in Input supply to the regulator; connect high-quality bypass capacitor(s) directly to this pin and PGND, with IN to PGND limited to -0.3 V to 40 V.
4 EN/UVLO input Enable pin that must not float (high = on, low = off); it can be tied to VIN, and its precision input allows adjustable UVLO through an external resistor divider, with EN to AGND limited to -0.3 V to VIN + 0.3 V.
5 CTRL1 input Logic-level control input for device/system configuration (see truth table), with CTRL1 to AGND limited to -0.3 V to 6 V.
6 CTRL2 input Logic-level control input for device/system configuration (see truth table), with CTRL2 to AGND limited to -0.3 V to 6 V.
7 DP_OUT bidirectional DP data line connected to the USB host controller, with DP_OUT to AGND limited to -0.3 V to 6 V.
8 DM_OUT bidirectional DM data line connected to the USB host controller, with DM_OUT to AGND limited to -0.3 V to 6 V.
9 RT/SYNC input Resistor timing pin that sets the switching frequency (300 kHz to 2.2 MHz) or external clock synchronization input, with RT/SYNC to AGND limited to -0.3 V to 6 V.
10 LS_GD output Gate driver output for the external NMOS, with LS_GD limited to -0.3 V to 18 V.
11 IMON passive External resistor sets the maximum cable-compensation voltage at full load current, with IMON to AGND limited to -0.3 V to 6 V.
12 ILIMIT passive External resistor sets the current-limit threshold (see table 10-2), with ILIMIT to AGND limited to -0.3 V to 6 V.
13 CSN/OUT input Negative input of the current-sense amplifier and buck output used for internal voltage regulation, with CSN to AGND limited to -0.3 V to 20 V.
14 CSP input Positive input of the current-sense amplifier, with CSP to AGND limited to -0.3 V to 20 V.
15 BUS input VBUS discharge input to be connected to VBUS on the USB connector, with BUS to AGND limited to -0.3 V to 18 V.
16 AGND power_in Analog ground and reference for internal references and logic; all electrical parameters are measured with respect to this pin, so connect it to system ground on the PCB.
17 DM_IN bidirectional DM data line connected to the USB connector; for TPS25832A-Q1, DP_IN/DM_IN to AGND is limited to -0.3 V to 7 V and short-to-VBAT protection is not supported.
18 DP_IN bidirectional DP data line connected to the USB connector; for TPS25832A-Q1, DP_IN/DM_IN to AGND is limited to -0.3 V to 7 V and short-to-VBAT protection is not supported.
19 CC2 bidirectional Analog input/output connected to the Type-C CC2 pin; for TPS25832A-Q1, CC1/CC2 to AGND is limited to -0.3 V to 7 V and short-to-VBAT protection is not supported.
20 CC1 bidirectional Analog input/output connected to the Type-C CC1 pin; for TPS25832A-Q1, CC1/CC2 to AGND is limited to -0.3 V to 7 V and short-to-VBAT protection is not supported.
21 VCC power_out Output of the internal bias supply used for internal control circuits; connect a high-quality 2.2-µF capacitor from this pin to GND, with VCC to AGND limited to -0.3 V to 6 V.
22 POL output Active-low open-drain output indicating which Type-C CC pin is connected to the cable CC line (asserted when CC2 is connected), giving the cable orientation needed to mux the super speed lines; limited to -0.3 V to 6 V.
23 LD_DET output Active-low open-drain output asserted when a Type-C UFP is identified on the CC lines, limited to -0.3 V to 6 V.
24 FAULT output Active-low open-drain output asserted during fault conditions (see table 10-4), limited to -0.3 V to 6 V.
25 PGND power_in Power ground; connect to system ground and AGND, and to the bypass capacitor with short wide traces.
26 PGND power_in Power ground; connect to system ground and AGND, and to the bypass capacitor with short wide traces.
27 PGND power_in Power ground; connect to system ground and AGND, and to the bypass capacitor with short wide traces.
28 SW power_out Switching output of the regulator, internally connected to the HS FET source and LS FET drain; connect to the power inductor, with SW to PGND limited to -0.3 V to VIN + 0.3 V (-3.5 V to 40 V for transients under 10 ns).
29 SW power_out Switching output of the regulator, internally connected to the HS FET source and LS FET drain; connect to the power inductor, with SW to PGND limited to -0.3 V to VIN + 0.3 V (-3.5 V to 40 V for transients under 10 ns).
30 SW power_out Switching output of the regulator, internally connected to the HS FET source and LS FET drain; connect to the power inductor, with SW to PGND limited to -0.3 V to VIN + 0.3 V (-3.5 V to 40 V for transients under 10 ns).
31 SW power_out Switching output of the regulator, internally connected to the HS FET source and LS FET drain; connect to the power inductor, with SW to PGND limited to -0.3 V to VIN + 0.3 V (-3.5 V to 40 V for transients under 10 ns).
32 BOOT passive Bootstrap capacitor connection for the HS FET driver; connect a high-quality 100-nF capacitor from this pin to SW, with BOOT to SW limited to -0.3 V to 6 V.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package QFN-32(5x5)
Category Power Management (PMIC)
Pins 33

CAD (KiCad official)

  • Symbol: TPS25832AQWRHBRQ1
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: QFN-32(5x5) (KiCad packages3D, STEP)
  • 3D model files: tps25832aqwrhbrq1-etched.step / tps25832aqwrhbrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps25832aqwrhbrq1.step / tps25832aqwrhbrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (76 pp, sha256 9069fce1d6b72633, retrieved 2026-10-11, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF