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TPS25830QWRHBRQ1

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Texas Instruments Power Management - Specialized, VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TPS25830QWRHBRQ1

Texas Instruments · Power Management - Specialized · VQFN-32-EP(5x5)

TPS25830QWRHBRQ1 from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN power_in Input supply to the regulator; connect a high-quality bypass capacitor(s) directly to this pin and PGND.
2 IN power_in Input supply to the regulator; connect a high-quality bypass capacitor(s) directly to this pin and PGND.
3 IN power_in Input supply to the regulator; connect a high-quality bypass capacitor(s) directly to this pin and PGND.
4 EN/UVLO input Enable pin that must not float: high turns the device on, low turns it off, and a precision enable input allows adjustable UVLO via an external resistor divider; it can be tied to VIN.
5 CTRL1 input Logic-level control input for device/system configuration (see Truth Table).
6 CTRL2 input Logic-level control input for device/system configuration (see Truth Table).
7 DP_OUT passive DP data line; connect to USB host controller (TPS25830-Q1 only).
8 DM_OUT passive DM data line; connect to USB host controller (TPS25830-Q1 only).
9 RT/SYNC input Resistor timing or external clock input; an external resistor to ground sets the switching frequency, and a clock pulled above the PLL upper threshold synchronizes the regulator.
10 LS_GD output External NMOS gate driver; for TPS25830-Q1 it must be pulled up through a 2.2-kΩ resistor under average current limit mode.
11 IMON passive External resistor used to set the maximum cable compensation voltage at full load current.
12 ILIMIT passive External resistor used to set the current-limit threshold.
13 CSN/OUT input Negative input of the current sense amplifier, also the buck output used for internal voltage regulation.
14 CSP input Positive input of the current sense amplifier.
15 BUS input VBUS discharge input; connect to VBUS on the USB connector.
16 AGND power_in Analog ground terminal and ground reference for internal references and logic; all electrical parameters are measured with respect to this pin and it should be connected to system ground.
17 DM_IN passive DM data line; connect to the USB connector.
18 DP_IN passive DP data line; connect to the USB connector.
19 CC2 bidirectional Analog input and output; connect to Type-C CC2 pin.
20 CC1 bidirectional Analog input and output; connect to Type-C CC1 pin.
21 VCC power_out Output of the internal bias supply used for internal control circuits; connect a high-quality 2.2-µF capacitor from this pin to GND.
22 POL output Active-LOW open-drain output that signals which Type-C CC pin is connected to the CC line, giving the cable orientation for super-speed muxing.
23 LD_DET output Active-LOW open-drain output asserted when a Type-C UFP is identified on the CC lines.
24 FAULT output Active-LOW open-drain output asserted during fault conditions (see Table 10-4).
25 PGND power_in Power ground terminal; connect to system ground and AGND with a bypass capacitor on short, wide traces.
26 PGND power_in Power ground terminal; connect to system ground and AGND with a bypass capacitor on short, wide traces.
27 PGND power_in Power ground terminal; connect to system ground and AGND with a bypass capacitor on short, wide traces.
28 SW power_out Switching output of the regulator, internally connected to the HS FET source and LS FET drain; connect to the power inductor.
29 SW power_out Switching output of the regulator, internally connected to the HS FET source and LS FET drain; connect to the power inductor.
30 SW power_out Switching output of the regulator, internally connected to the HS FET source and LS FET drain; connect to the power inductor.
31 SW power_out Switching output of the regulator, internally connected to the HS FET source and LS FET drain; connect to the power inductor.
32 BOOT power_out Bootstrap capacitor connection for the HS FET driver; connect a high-quality 100-nF capacitor from this pin to the SW pin.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-32-EP(5x5)
Category Power Management (PMIC)
Pins 33

CAD (KiCad official)

  • Symbol: TPS25830QWRHBRQ1
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: tps25830qwrhbrq1-etched.step / tps25830qwrhbrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps25830qwrhbrq1.step / tps25830qwrhbrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (82 pp, sha256 e1e87c1136f84629, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF