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TPS25830QWRHBRQ1
Public Made by Adomby adom
Texas Instruments Power Management - Specialized, VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+70@@ -0,0 +1,70 @@+# TPS25830QWRHBRQ1++**Texas Instruments** · Power Management - Specialized · VQFN-32-EP(5x5)++TPS25830QWRHBRQ1 from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | IN | power_in | Input supply to the regulator; connect a high-quality bypass capacitor(s) directly to this pin and PGND. |+| 2 | IN | power_in | Input supply to the regulator; connect a high-quality bypass capacitor(s) directly to this pin and PGND. |+| 3 | IN | power_in | Input supply to the regulator; connect a high-quality bypass capacitor(s) directly to this pin and PGND. |+| 4 | EN/UVLO | input | Enable pin that must not float: high turns the device on, low turns it off, and a precision enable input allows adjustable UVLO via an external resistor divider; it can be tied to VIN. |+| 5 | CTRL1 | input | Logic-level control input for device/system configuration (see Truth Table). |+| 6 | CTRL2 | input | Logic-level control input for device/system configuration (see Truth Table). |+| 7 | DP_OUT | passive | DP data line; connect to USB host controller (TPS25830-Q1 only). |+| 8 | DM_OUT | passive | DM data line; connect to USB host controller (TPS25830-Q1 only). |+| 9 | RT/SYNC | input | Resistor timing or external clock input; an external resistor to ground sets the switching frequency, and a clock pulled above the PLL upper threshold synchronizes the regulator. |+| 10 | LS_GD | output | External NMOS gate driver; for TPS25830-Q1 it must be pulled up through a 2.2-kΩ resistor under average current limit mode. |+| 11 | IMON | passive | External resistor used to set the maximum cable compensation voltage at full load current. |+| 12 | ILIMIT | passive | External resistor used to set the current-limit threshold. |+| 13 | CSN/OUT | input | Negative input of the current sense amplifier, also the buck output used for internal voltage regulation. |+| 14 | CSP | input | Positive input of the current sense amplifier. |+| 15 | BUS | input | VBUS discharge input; connect to VBUS on the USB connector. |+| 16 | AGND | power_in | Analog ground terminal and ground reference for internal references and logic; all electrical parameters are measured with respect to this pin and it should be connected to system ground. |+| 17 | DM_IN | passive | DM data line; connect to the USB connector. |+| 18 | DP_IN | passive | DP data line; connect to the USB connector. |+| 19 | CC2 | bidirectional | Analog input and output; connect to Type-C CC2 pin. |+| 20 | CC1 | bidirectional | Analog input and output; connect to Type-C CC1 pin. |+| 21 | VCC | power_out | Output of the internal bias supply used for internal control circuits; connect a high-quality 2.2-µF capacitor from this pin to GND. |+| 22 | POL | output | Active-LOW open-drain output that signals which Type-C CC pin is connected to the CC line, giving the cable orientation for super-speed muxing. |+| 23 | LD_DET | output | Active-LOW open-drain output asserted when a Type-C UFP is identified on the CC lines. |+| 24 | FAULT | output | Active-LOW open-drain output asserted during fault conditions (see Table 10-4). |+| 25 | PGND | power_in | Power ground terminal; connect to system ground and AGND with a bypass capacitor on short, wide traces. |+| 26 | PGND | power_in | Power ground terminal; connect to system ground and AGND with a bypass capacitor on short, wide traces. |+| 27 | PGND | power_in | Power ground terminal; connect to system ground and AGND with a bypass capacitor on short, wide traces. |+| 28 | SW | power_out | Switching output of the regulator, internally connected to the HS FET source and LS FET drain; connect to the power inductor. |+| 29 | SW | power_out | Switching output of the regulator, internally connected to the HS FET source and LS FET drain; connect to the power inductor. |+| 30 | SW | power_out | Switching output of the regulator, internally connected to the HS FET source and LS FET drain; connect to the power inductor. |+| 31 | SW | power_out | Switching output of the regulator, internally connected to the HS FET source and LS FET drain; connect to the power inductor. |+| 32 | BOOT | power_out | Bootstrap capacitor connection for the HS FET driver; connect a high-quality 100-nF capacitor from this pin to the SW pin. |+| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-32-EP(5x5) |+| Category | Power Management (PMIC) |+| Pins | 33 |++## CAD (KiCad official)++- Symbol: `TPS25830QWRHBRQ1`+- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm`+- 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)+- 3D model files: `tps25830qwrhbrq1-etched.step` / `tps25830qwrhbrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps25830qwrhbrq1.step` / `tps25830qwrhbrq1.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps25831-q1) (82 pp, sha256 `e1e87c1136f84629`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tps25830qwrhbrq1-datasheet.pdf)
page.jsonadded+351@@ -0,0 +1,351 @@+{+ "slug": "tps25830qwrhbrq1",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Power Management - Specialized, VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "power management (pmic)",+ "tps25830qwrhbrq1",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "tps25830qwrhbrq1.kicad_sym",+ "tps25830qwrhbrq1.kicad_mod",+ "tps25830qwrhbrq1.glb",+ "tps25830qwrhbrq1.step",+ "tps25830qwrhbrq1.lbr",+ "docs/hero.png",+ "docs/tps25830qwrhbrq1-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "tps25830qwrhbrq1-hero.glb",+ "tps25830qwrhbrq1-hero.overlay.json"+ ],+ "component": {+ "mpn": "TPS25830QWRHBRQ1",+ "manufacturer": "Texas Instruments",+ "package": "VQFN-32-EP(5x5)",+ "pin_count": 33,+ "category": "Power Management (PMIC)",+ "subcategory": "Power Management - Specialized",+ "datasheet": "https://www.ti.com/cn/lit/gpn/tps25831-q1",+ "parts": {+ "symbol": "tps25830qwrhbrq1.kicad_sym",+ "footprint": "tps25830qwrhbrq1.kicad_mod",+ "model_3d": "tps25830qwrhbrq1-hero.glb",+ "model_3d_plain": "tps25830qwrhbrq1.glb",+ "model_3d_step": "tps25830qwrhbrq1-etched.step",+ "model_3d_step_plain": "tps25830qwrhbrq1.step",+ "lbr": "tps25830qwrhbrq1.lbr"+ },+ "distributor_links": {+ "lcsc": "C2876673",+ "digikey": "296-TPS25830QWRHBRQ1TR-ND",+ "mouser": "595-TPS25830QWRHBRQ1"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T17:10:41Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-TPS25830QWRHBRQ1TR-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-TPS25830QWRHBRQ1",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "IN",+ "type": "power_in",+ "description": "Input supply to the regulator; connect a high-quality bypass capacitor(s) directly to this pin and PGND."+ },+ {+ "number": "2",+ "name": "IN",+ "type": "power_in",+ "description": "Input supply to the regulator; connect a high-quality bypass capacitor(s) directly to this pin and PGND."+ },+ {+ "number": "3",+ "name": "IN",+ "type": "power_in",+ "description": "Input supply to the regulator; connect a high-quality bypass capacitor(s) directly to this pin and PGND."+ },+ {+ "number": "4",+ "name": "EN/UVLO",+ "type": "input",+ "description": "Enable pin that must not float: high turns the device on, low turns it off, and a precision enable input allows adjustable UVLO via an external resistor divider; it can be tied to VIN."+ },+ {+ "number": "5",+ "name": "CTRL1",+ "type": "input",+ "description": "Logic-level control input for device/system configuration (see Truth Table)."+ },+ {+ "number": "6",+ "name": "CTRL2",+ "type": "input",+ "description": "Logic-level control input for device/system configuration (see Truth Table)."+ },+ {+ "number": "7",+ "name": "DP_OUT",+ "type": "passive",+ "description": "DP data line; connect to USB host controller (TPS25830-Q1 only)."+ },+ {+ "number": "8",+ "name": "DM_OUT",+ "type": "passive",+ "description": "DM data line; connect to USB host controller (TPS25830-Q1 only)."+ },+ {+ "number": "9",+ "name": "RT/SYNC",+ "type": "input",+ "description": "Resistor timing or external clock input; an external resistor to ground sets the switching frequency, and a clock pulled above the PLL upper threshold synchronizes the regulator."+ },+ {+ "number": "10",+ "name": "LS_GD",+ "type": "output",+ "description": "External NMOS gate driver; for TPS25830-Q1 it must be pulled up through a 2.2-kΩ resistor under average current limit mode."+ },+ {+ "number": "11",+ "name": "IMON",+ "type": "passive",+ "description": "External resistor used to set the maximum cable compensation voltage at full load current."+ },+ {+ "number": "12",+ "name": "ILIMIT",+ "type": "passive",+ "description": "External resistor used to set the current-limit threshold."+ },+ {+ "number": "13",+ "name": "CSN/OUT",+ "type": "input",+ "description": "Negative input of the current sense amplifier, also the buck output used for internal voltage regulation."+ },+ {+ "number": "14",+ "name": "CSP",+ "type": "input",+ "description": "Positive input of the current sense amplifier."+ },+ {+ "number": "15",+ "name": "BUS",+ "type": "input",+ "description": "VBUS discharge input; connect to VBUS on the USB connector."+ },+ {+ "number": "16",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground terminal and ground reference for internal references and logic; all electrical parameters are measured with respect to this pin and it should be connected to system ground."+ },+ {+ "number": "17",+ "name": "DM_IN",+ "type": "passive",+ "description": "DM data line; connect to the USB connector."+ },+ {+ "number": "18",+ "name": "DP_IN",+ "type": "passive",+ "description": "DP data line; connect to the USB connector."+ },+ {+ "number": "19",+ "name": "CC2",+ "type": "bidirectional",+ "description": "Analog input and output; connect to Type-C CC2 pin."+ },+ {+ "number": "20",+ "name": "CC1",+ "type": "bidirectional",+ "description": "Analog input and output; connect to Type-C CC1 pin."+ },+ {+ "number": "21",+ "name": "VCC",+ "type": "power_out",+ "description": "Output of the internal bias supply used for internal control circuits; connect a high-quality 2.2-µF capacitor from this pin to GND."+ },+ {+ "number": "22",+ "name": "POL",+ "type": "output",+ "description": "Active-LOW open-drain output that signals which Type-C CC pin is connected to the CC line, giving the cable orientation for super-speed muxing."+ },+ {+ "number": "23",+ "name": "LD_DET",+ "type": "output",+ "description": "Active-LOW open-drain output asserted when a Type-C UFP is identified on the CC lines."+ },+ {+ "number": "24",+ "name": "FAULT",+ "type": "output",+ "description": "Active-LOW open-drain output asserted during fault conditions (see Table 10-4)."+ },+ {+ "number": "25",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground terminal; connect to system ground and AGND with a bypass capacitor on short, wide traces."+ },+ {+ "number": "26",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground terminal; connect to system ground and AGND with a bypass capacitor on short, wide traces."+ },+ {+ "number": "27",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground terminal; connect to system ground and AGND with a bypass capacitor on short, wide traces."+ },+ {+ "number": "28",+ "name": "SW",+ "type": "power_out",+ "description": "Switching output of the regulator, internally connected to the HS FET source and LS FET drain; connect to the power inductor."+ },+ {+ "number": "29",+ "name": "SW",+ "type": "power_out",+ "description": "Switching output of the regulator, internally connected to the HS FET source and LS FET drain; connect to the power inductor."+ },+ {+ "number": "30",+ "name": "SW",+ "type": "power_out",+ "description": "Switching output of the regulator, internally connected to the HS FET source and LS FET drain; connect to the power inductor."+ },+ {+ "number": "31",+ "name": "SW",+ "type": "power_out",+ "description": "Switching output of the regulator, internally connected to the HS FET source and LS FET drain; connect to the power inductor."+ },+ {+ "number": "32",+ "name": "BOOT",+ "type": "power_out",+ "description": "Bootstrap capacitor connection for the HS FET driver; connect a high-quality 100-nF capacitor from this pin to the SW pin."+ },+ {+ "number": "33",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The thermal pad is the exposed pad under the package; it is not a numbered pin in Table 7-1 or the F; Corner anchors shown in Figure 7-1 are not signal pins and are not numbered in Table 7-1. Note 2 say; Table 7-1 gives the type of BOOT and SW only as 'P' (power). The power_out classification is an infe",+ "exposed pad 33 added from the footprint"+ ],+ "pages_sent": 11,+ "cost_usd": 0.0936,+ "at": "2026-10-08T17:10:24"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tps25831-q1",+ "pages": 82,+ "sha256": "e1e87c1136f84629",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 33,+ "described": 33,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "tps25830qwrhbrq1.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 5,+ 5,+ 0.875+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "5fa713ea46b36980895812ed853577889b7cb06d275041a39b99bc0be305dc79",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "tps25830qwrhbrq1-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 5,+ 5,+ 0.875+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "0e381c2c739f7e7b285c5ac6d3139babe79f9b91c73d2a7f00eea67f0bdbe0f8",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}