component

TPS25750SRSMR

Public Made by Adom

by adom

Texas Instruments Power Management - Specialized, VQFN-32(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TPS25750SRSMR

Texas Instruments · Power Management - Specialized · VQFN-32(4x4)

TPS25750SRSMR from Texas Instruments, in a VQFN-32(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 LDO_3V3 power_out Output of the supply switched from VIN_3V3 or the VBUS LDO; bypass with capacitance CLDO_3V3 to GND.
2 ADCIN1 input Configuration input connected to a resistor divider from LDO_3V3; absolute maximum range is -0.3 V to 4 V.
3 ADCIN2 input Configuration input connected to a resistor divider from LDO_3V3; absolute maximum range is -0.3 V to 4 V.
4 LDO_1V5 power_out Output of the CORE LDO; bypass with capacitance CLDO_1V5 to GND, and this pin cannot source current to external circuits.
5 GPIO0 bidirectional General-purpose digital I/O; tie to ground when unused.
6 GPIO1 bidirectional General-purpose digital I/O; tie to ground when unused.
7 GPIO2 bidirectional General-purpose digital I/O; tie to ground when unused.
8 I2Cs_SDA bidirectional I2C slave serial data, open-drain input/output; tie to pull-up voltage through a resistor, or ground if unused.
9 I2Cs_SCL input I2C slave serial clock input; tie to pull-up voltage through a resistor, or ground if unused.
10 I2Cs_IRQ output I2C slave interrupt, active low; connect to an external voltage through a pull-up resistor, may be re-configured to GPIO10, and tie to ground when unused.
11 GND power_in Ground; connect to the ground plane.
12 GND power_in Ground; connect to the ground plane.
13 GPIO11 output General-purpose digital output; tie to ground when unused.
14 GND power_in Ground; connect to the ground plane.
15 I2Cm_SDA bidirectional I2C master serial data, open-drain input/output; tie to pull-up voltage through a resistor when used or unused.
16 I2Cm_SCL output I2C master serial clock, open-drain output; tie to pull-up voltage through a resistor when used or unused.
17 I2Cm_IRQ input I2C master interrupt, active low; connect to an external voltage through a pull-up resistor, tie to ground when unused, and may be re-configured to GPIO12.
18 GPIO3 bidirectional General-purpose digital I/O; tie to ground when unused.
19 VSYS power_in High-voltage sinking node used to implement reverse-current protection (RCP) for the external sinking paths controlled by GATE_VSYS.
20 GATE_VSYS output Drives the gate of an N-channel MOSFET whose source is tied to VSYS; absolute maximum output voltage is 40 V.
21 GATE_VBUS output Drives the gate of an N-channel MOSFET whose source is tied to VBUS; absolute maximum output voltage is 40 V.
22 GPIO4 (USB_P) bidirectional General-purpose digital I/O that may be connected to D+ for BC1.2 support; tie to ground when unused.
23 GPIO5 (USB_N) bidirectional General-purpose digital I/O that may be connected to D- for BC1.2 support; tie to ground when unused.
24 CC1 bidirectional I/O for USB Type-C; filter noise with the recommended capacitor to GND (CCCy); absolute maximum range is -0.5 V to 26 V.
25 CC2 bidirectional I/O for USB Type-C; filter noise with the recommended capacitor to GND (CCCy); absolute maximum range is -0.5 V to 26 V.
26 VBUS power_in 5-V to 20-V input; bypass with capacitance CVBUS to GND.
27 VBUS power_in 5-V to 20-V input; bypass with capacitance CVBUS to GND.
28 PP5V power_in 5-V system supply to VBUS and supply for the CCy pins as VCONN; absolute maximum is 6 V.
29 PP5V power_in 5-V system supply to VBUS and supply for the CCy pins as VCONN; absolute maximum is 6 V.
30 GPIO7 bidirectional General-purpose digital I/O; tie to ground when unused.
31 GPIO6 bidirectional General-purpose digital I/O; tie to ground when unused.
32 VIN_3V3 power_in Supply for core circuitry and I/O; bypass with capacitance CVIN_3V3 to GND, with absolute maximum of 4 V.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-32(4x4)
Category Power Management (PMIC)
Pins 33

CAD (KiCad official)

  • Symbol: TPS25750SRSMR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_4x4mm_P0.4mm_EP2.9x2.9mm
  • 3D model: VQFN-32(4x4) (KiCad packages3D, STEP)
  • 3D model files: tps25750srsmr-etched.step / tps25750srsmr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps25750srsmr.step / tps25750srsmr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (79 pp, sha256 a67213f1bd1b7c0b, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF