component
TPS2375D
Public Made by Adomby adom
Texas Instruments Power Over Ethernet (PoE) Controllers, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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TPS2375D
Texas Instruments · Power Over Ethernet (PoE) Controllers · SOIC-8
TPS2375D from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ILIM | output | Connect a resistor from ILIM to VSS to set the start-up inrush current limit, with R(ILIM) practically limited to 62.5 kΩ to 500 kΩ (178 kΩ recommended for legacy PSE compatibility), and the pin must not be left open or shorted to VSS. |
| 2 | CLASS | output | Connect an external classification resistor from CLASS to VSS per Table 1 (255 Ω to 4420 Ω), drawing current only when VDD is between 13 V and 21 V, and the CLASS pin must not be shorted to ground. |
| 3 | DET | output | Connect a 24.9-kΩ ±1% detection resistor from DET to VDD for valid PD detection, which is connected across the line only when V(VDD) is between 1.4 V and 11.3 V. |
| 4 | VSS | power_in | Input supply negative rail and local ground for the TPS2375, serving as the return line from the PSE; per the layout notes, pin 4 has the lowest thermal resistance to the die. |
| 5 | RTN | output | Switched negative power rail (output-side return) used as the low-side reference for the load, with recommended operating voltage 0 to 57 V, sinking current 0 to 350 mA, and absolute maximum SOA limited to V(RTN) = 80 V and I(RTN) = 515 mA. |
| 6 | PG | output | Open-drain, active-high power-good output that goes high-impedance when the pass MOSFET is on and not in inrush limiting, requires a pullup resistor or other interface, and is rated for 0 to 2 mA sinking current with at least 4 V between VDD and RTN. |
| 7 | NC | unconnected | No internal connection on the TPS2375 (this pin is the UVLO input only on the TPS2376 and is not connected internally on the TPS2375). |
| 8 | VDD | power_in | Positive input supply from the rectified PSE line, with recommended input voltage range 0 to 57 V, and absolute maximum of 100 V referenced to VSS. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
TPS2375D - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
tps2375d-etched.step/tps2375d-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps2375d.step/tps2375d.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (28 pp, sha256
6559d81e1161e551, retrieved 2026-10-09, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).