TPS23757PWR

{
  "slug": "tps23757pwr",
  "version": "0.1.0",
  "type": "component",
  "description": "Texas Instruments Power Over Ethernet (PoE) Controllers, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "power management (pmic)",
    "tps23757pwr",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
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    "README.md",
    "tps23757pwr.kicad_sym",
    "tps23757pwr.kicad_mod",
    "tps23757pwr.glb",
    "tps23757pwr.step",
    "tps23757pwr.lbr",
    "docs/hero.png",
    "docs/tps23757pwr-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
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    "tps23757pwr-hero.overlay.json"
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  "component": {
    "mpn": "TPS23757PWR",
    "manufacturer": "Texas Instruments",
    "package": "TSSOP-20",
    "pin_count": 20,
    "category": "Power Management (PMIC)",
    "subcategory": "Power Over Ethernet (PoE) Controllers",
    "datasheet": "https://www.ti.com/lit/ds/symlink/tps23757.pdf",
    "parts": {
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      "footprint": "tps23757pwr.kicad_mod",
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      "model_3d_plain": "tps23757pwr.glb",
      "model_3d_step": "tps23757pwr-etched.step",
      "model_3d_step_plain": "tps23757pwr.step",
      "lbr": "tps23757pwr.lbr"
    },
    "distributor_links": {
      "lcsc": "C2866869",
      "digikey": "296-46377-2-ND",
      "mouser": "595-TPS23757PWR"
    },
    "distributor_check": {
      "checked_at": "2026-10-11T17:08:37Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "296-46377-2-ND",
        "status": "found",
        "lifecycle": "Active"
      },
      "mouser": {
        "pn": "595-TPS23757PWR",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "CTL",
        "type": "input",
        "description": "Control loop input to the PWM, typically driven by output regulation feedback such as an optocoupler, with VB as its pull-up source and an internal divider of about 100 kΩ to ARTN; pulling it below VZDC stops GATE switching."
      },
      {
        "number": "2",
        "name": "VB",
        "type": "power_in",
        "description": "Internal 5.1 V regulated bias rail (5.10 V typical, 4.8 V to 5.25 V over 6.5 V ≤ VC ≤ 18 V and 0 to 5 mA load) for the dc/dc control circuits and feedback optocoupler, typically bypassed with 0.1 μF to ARTN."
      },
      {
        "number": "3",
        "name": "CS",
        "type": "bidirectional",
        "description": "Current-sense input for the dc/dc switching MOSFET, connected to the high side of RCS, where the voltage above VCSMAX terminates the GATE on-time; absolute maximum is -0.3 V to VB with respect to [ARTN, COM]."
      },
      {
        "number": "4",
        "name": "COM",
        "type": "power_in",
        "description": "Gate driver return that should be connected to ARTN and RTN for most applications."
      },
      {
        "number": "5",
        "name": "GATE",
        "type": "output",
        "description": "Gate drive output for the main dc/dc converter switching MOSFET, held low when the converter is disabled, with absolute maximum of -0.3 V to VC+0.3 V to [ARTN, COM]."
      },
      {
        "number": "6",
        "name": "VC",
        "type": "bidirectional",
        "description": "DC/DC converter bias supply that must be connected to a bias source in normal operation and requires a minimum 0.47 μF ceramic capacitor to ARTN at the pin plus a larger capacitor for startup, with absolute maximum of -0.3 V to 19 V to [ARTN, COM]."
      },
      {
        "number": "7",
        "name": "GAT2",
        "type": "output",
        "description": "Second gate drive output for a second dc/dc switching MOSFET (such as a flyback synchronous rectifier), which is held low when the converter is disabled and goes high-impedance when DT is tied to VB."
      },
      {
        "number": "8",
        "name": "ARTN",
        "type": "power_in",
        "description": "Quiet analog return for the dc/dc converter, to be tied to COM and RTN for most applications."
      },
      {
        "number": "9",
        "name": "RTN",
        "type": "power_out",
        "description": "Output of the PoE hotswap MOSFET, with a recommended continuous RTN current of 400 mA at TJ ≤ 125 °C and an absolute maximum of -0.3 V to 100 V to [ARTN, COM] on the pin."
      },
      {
        "number": "10",
        "name": "VSS",
        "type": "power_in",
        "description": "Negative power rail derived from the PoE source and reference for the PoE interface circuits, clamped to a diode drop above RTN by the hotswap switch."
      },
      {
        "number": "11",
        "name": "VDD1",
        "type": "input",
        "description": "Source of dc/dc converter startup current, which may be connected to VDD or isolated by a diode from VDD for PoE priority operation; recommended input range is 0 V to 57 V."
      },
      {
        "number": "12",
        "name": "VDD",
        "type": "power_in",
        "description": "Positive PoE input power rail that powers the PoE interface, to be bypassed to VSS with 0.1 μF and protected with a TVS such as SMAJ58A; recommended input range is 0 V to 57 V."
      },
      {
        "number": "13",
        "name": "DEN",
        "type": "bidirectional",
        "description": "Detection and enable pin that takes a 24.9 kΩ resistor to VDD for the PoE detection signature, and pulling it to VSS during powered operation turns the hotswap MOSFET and class regulator off."
      },
      {
        "number": "14",
        "name": "PPD",
        "type": "input",
        "description": "Powered-device pin where raising VPPD - VVSS above 1.55 V enables the hotswap MOSFET and activates APb, with a 5 μA internal pull-down, and it should be tied to VSS or left open when unused."
      },
      {
        "number": "15",
        "name": "CLS",
        "type": "input",
        "description": "Classification current programming pin, where a resistor from CLS to VSS sets the class per Table 1 (1270 Ω for class 0 up to 63.4 Ω for class 4)."
      },
      {
        "number": "16",
        "name": "DT",
        "type": "input",
        "description": "Dead-time programming pin, where a resistor from DT to ARTN sets the GATE to GAT2 delay, and tying DT to VB sets dead time to 0 and turns GAT2 off."
      },
      {
        "number": "17",
        "name": "APD",
        "type": "input",
        "description": "Adapter priority detect pin, where raising VAPD - VARTN above 1.5 V disables the internal hotswap MOSFET, turns class off and forces APb active, and it should be tied to ARTN when unused."
      },
      {
        "number": "18",
        "name": "BLNK",
        "type": "input",
        "description": "Current-sense blanking programming pin, which is tied to ARTN for the internally set blanking period or connected to ARTN through a resistor (0 to 350 kΩ) for a programmed blanking period."
      },
      {
        "number": "19",
        "name": "FRS",
        "type": "input",
        "description": "Frequency and synchronization pin, where a resistor to ARTN programs the converter switching frequency and short ac-coupled pulses (25 ns minimum width) can synchronize the converter to an external timing source."
      },
      {
        "number": "20",
        "name": "APb",
        "type": "output",
        "description": "Active-low output indicating that PPD (first level) or APD is active, intended to drive the diode side of an optocoupler and referenced to ARTN, with absolute maximum of -0.3 V to 19 V to [ARTN, COM]."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The TYPE column is blank for these pins in the PIN FUNCTIONS table. Types were assigned by engineeri; Pin numbers were taken from the PIN FUNCTIONS table on page 7. The PWP top-view drawing on page 6 ha"
        ],
        "pages_sent": 12,
        "cost_usd": 0.0826,
        "at": "2026-10-11T17:08:21"
      },
      "datasheet": {
        "url": "https://www.ti.com/lit/ds/symlink/tps23757.pdf",
        "pages": 40,
        "sha256": "ff0697cc828e910d",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 20,
        "described": 20,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
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        "seat": "z = 0",
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        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
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        "checked": "2026-10-11",
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        "zmin_mm": -0.0,
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        "sha256": "022d343d2c66f75eae7f637ff7a5d1e44780b1365c52a96c3e99dede2d8b7819",
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  }
}