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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

TPS23757PWR

Texas Instruments · Power Over Ethernet (PoE) Controllers · TSSOP-20

TPS23757PWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	CTL	input	Control loop input to the PWM, typically driven by output regulation feedback such as an optocoupler, with VB as its pull-up source and an internal divider of about 100 kΩ to ARTN; pulling it below VZDC stops GATE switching.
2	VB	power_in	Internal 5.1 V regulated bias rail (5.10 V typical, 4.8 V to 5.25 V over 6.5 V ≤ VC ≤ 18 V and 0 to 5 mA load) for the dc/dc control circuits and feedback optocoupler, typically bypassed with 0.1 μF to ARTN.
3	CS	bidirectional	Current-sense input for the dc/dc switching MOSFET, connected to the high side of RCS, where the voltage above VCSMAX terminates the GATE on-time; absolute maximum is -0.3 V to VB with respect to [ARTN, COM].
4	COM	power_in	Gate driver return that should be connected to ARTN and RTN for most applications.
5	GATE	output	Gate drive output for the main dc/dc converter switching MOSFET, held low when the converter is disabled, with absolute maximum of -0.3 V to VC+0.3 V to [ARTN, COM].
6	VC	bidirectional	DC/DC converter bias supply that must be connected to a bias source in normal operation and requires a minimum 0.47 μF ceramic capacitor to ARTN at the pin plus a larger capacitor for startup, with absolute maximum of -0.3 V to 19 V to [ARTN, COM].
7	GAT2	output	Second gate drive output for a second dc/dc switching MOSFET (such as a flyback synchronous rectifier), which is held low when the converter is disabled and goes high-impedance when DT is tied to VB.
8	ARTN	power_in	Quiet analog return for the dc/dc converter, to be tied to COM and RTN for most applications.
9	RTN	power_out	Output of the PoE hotswap MOSFET, with a recommended continuous RTN current of 400 mA at TJ ≤ 125 °C and an absolute maximum of -0.3 V to 100 V to [ARTN, COM] on the pin.
10	VSS	power_in	Negative power rail derived from the PoE source and reference for the PoE interface circuits, clamped to a diode drop above RTN by the hotswap switch.
11	VDD1	input	Source of dc/dc converter startup current, which may be connected to VDD or isolated by a diode from VDD for PoE priority operation; recommended input range is 0 V to 57 V.
12	VDD	power_in	Positive PoE input power rail that powers the PoE interface, to be bypassed to VSS with 0.1 μF and protected with a TVS such as SMAJ58A; recommended input range is 0 V to 57 V.
13	DEN	bidirectional	Detection and enable pin that takes a 24.9 kΩ resistor to VDD for the PoE detection signature, and pulling it to VSS during powered operation turns the hotswap MOSFET and class regulator off.
14	PPD	input	Powered-device pin where raising VPPD - VVSS above 1.55 V enables the hotswap MOSFET and activates APb, with a 5 μA internal pull-down, and it should be tied to VSS or left open when unused.
15	CLS	input	Classification current programming pin, where a resistor from CLS to VSS sets the class per Table 1 (1270 Ω for class 0 up to 63.4 Ω for class 4).
16	DT	input	Dead-time programming pin, where a resistor from DT to ARTN sets the GATE to GAT2 delay, and tying DT to VB sets dead time to 0 and turns GAT2 off.
17	APD	input	Adapter priority detect pin, where raising VAPD - VARTN above 1.5 V disables the internal hotswap MOSFET, turns class off and forces APb active, and it should be tied to ARTN when unused.
18	BLNK	input	Current-sense blanking programming pin, which is tied to ARTN for the internally set blanking period or connected to ARTN through a resistor (0 to 350 kΩ) for a programmed blanking period.
19	FRS	input	Frequency and synchronization pin, where a resistor to ARTN programs the converter switching frequency and short ac-coupled pulses (25 ns minimum width) can synchronize the converter to an external timing source.
20	APb	output	Active-low output indicating that PPD (first level) or APD is active, intended to drive the diode side of an optocoupler and referenced to ARTN, with absolute maximum of -0.3 V to 19 V to [ARTN, COM].

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TSSOP-20
Category	Power Management (PMIC)
Pins	20

CAD (KiCad official)

Symbol: TPS23757PWR
Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
3D model: TSSOP-20 (KiCad packages3D, STEP)
3D model files: tps23757pwr-etched.step / tps23757pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps23757pwr.step / tps23757pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (40 pp, sha256 ff0697cc828e910d, retrieved 2026-10-11, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF