TPS2042DR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	GND	power_in	Ground reference for the device.
2	IN	power_in	Input voltage to the two high-side power switches, operating from 2.7 V to 5.5 V.
3	EN1	input	Enable input for power switch IN-OUT1; on the TPS2042 a logic low turns the switch on, and the enable is compatible with both TTL and CMOS logic levels.
4	EN2	input	Enable input for power switch IN-OUT2; on the TPS2042 a logic low turns the switch on, and the enable is compatible with both TTL and CMOS logic levels.
5	OC2	output	Open-drain overcurrent output for power switch IN-OUT2, asserted active low on overcurrent or overtemperature.
6	OUT2	power_out	Power-switch output for channel 2, a high-side N-channel MOSFET with a maximum on-state resistance of 135 mΩ at VI(IN) = 5 V.
7	OUT1	power_out	Power-switch output for channel 1, a high-side N-channel MOSFET with a maximum on-state resistance of 135 mΩ at VI(IN) = 5 V.
8	OC1	output	Open-drain overcurrent output for power switch IN-OUT1, asserted active low on overcurrent or overtemperature.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-8
Category	Power Management (PMIC)
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Input voltage range	VI(IN)	-0.3		6	V	All voltages with respect to GND (Note 1)	4
Output voltage range	VO(OUTx)	-0.3			V	Max is VI(IN) + 0.3 V; all voltages with respect to GND (Note 1)	4
Input voltage range enable	VI(ENx) or VI(ENx)	-0.3		6	V	All voltages with respect to GND (Note 1)	4
Operating virtual junction temperature range	TJ	-40		125	°C		4
Storage temperature range	Tstg	-65		150	°C		4
Lead temperature soldering				260	°C	1,6 mm (1/16 inch) from case for 10 seconds	4
Electrostatic discharge human body model				2	kV	MIL-STD-883C	4
Electrostatic discharge machine model				0.2	kV		4
Input voltage	VI(IN)	2.7		5.5	V		4
Input voltage enable	VI(ENx) or VI(ENx)	0		5.5	V		4
Continuous output current	IO(OUTx)	0		500	mA		4
Operating virtual junction temperature	TJ	-40		125	°C		4
Static drain-source on-state resistance, 5-V operation	rDS(on)		80	95	mΩ	VI(IN) = 5 V, IO = 0.5 A, TJ = 25°C	5
Static drain-source on-state resistance, 5-V operation	rDS(on)		90	120	mΩ	VI(IN) = 5 V, IO = 0.5 A, TJ = 85°C	5
Static drain-source on-state resistance, 5-V operation	rDS(on)		100	135	mΩ	VI(IN) = 5 V, IO = 0.5 A, TJ = 125°C	5
Static drain-source on-state resistance, 3.3-V operation	rDS(on)		85	105	mΩ	VI(IN) = 3.3 V, IO = 0.5 A, TJ = 25°C	5
Static drain-source on-state resistance, 3.3-V operation	rDS(on)		100	135	mΩ	VI(IN) = 3.3 V, IO = 0.5 A, TJ = 85°C	5
Static drain-source on-state resistance, 3.3-V operation	rDS(on)		115	150	mΩ	VI(IN) = 3.3 V, IO = 0.5 A, TJ = 125°C	5
High-level input voltage	VIH	2			V	2.7 V ≤ VI(IN) ≤ 5.5 V	5
Low-level input voltage	VIL			0.8	V	4.5 V ≤ VI(IN) ≤ 5.5 V	5
Low-level input voltage	VIL			0.4	V	2.7 V ≤ VI(IN) ≤ 4.5 V	5
Input current	II	-0.5		0.5	µA	TPS2042: VI(ENx) = 0 V or VI(ENx) = VI(IN)	5
Short-circuit output current	IOS	0.7	0.9	1.1	A	VI(IN) = 5 V, OUT connected to GND, device enable into short circuit	5
Supply current, no load, low-level output			0.015	1	µA	TJ = 25°C, VI(ENx) = VI(IN), TPS2042	6
Supply current, no load, low-level output				10	µA	-40°C ≤ TJ ≤ 125°C, VI(ENx) = VI(IN), TPS2042	6
Supply current, no load, high-level output			80	100	µA	TJ = 25°C, VI(ENx) = 0 V, TPS2042	6
Supply current, no load, high-level output				100	µA	-40°C ≤ TJ ≤ 125°C, VI(ENx) = 0 V, TPS2042	6
Leakage current OUT connected to ground				100	µA	-40°C ≤ TJ ≤ 125°C, VI(ENx) = VI(IN), TPS2042	6
Reverse leakage current				0.3	µA	IN = high, VI(EN) = 0 V, TJ = 25°C, TPS2042	6
Low-level input voltage (undervoltage lockout)		2		2.5	V		6
Sink current		10			mA	VO = 5 V (OCx), specified by design	6
Output low voltage	VOL(OCx)			0.5	V	IO = 5 mA	6
Off-state current				1	µA	VO = 5 V, VO = 3.3 V	6
Thermal resistance junction-to-ambient	RθJA		172		°C/W	SOIC package	16
Continuous total power dissipation rating				725	mW	D (SOIC) package, TA ≤ 25°C	4

CAD (KiCad official)

Symbol: TPS2042DR
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)
3D model files: tps2042dr-etched.step / tps2042dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps2042dr.step / tps2042dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (27 pp, sha256 317ebf8ca7ddb20d, retrieved 2026-11-06, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

TPS2042DR

Verified TPS2042DR

Verification log 1 record

3D Model

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Schematic Symbol

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Datasheet

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