component
TPS1120DR
Public Made by Adomby adom
Texas Instruments MOSFETs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 1d ago |
| viewers | 1d ago |
| package.json | 1d ago |
| page.json | 1d ago |
| README.md | 1d ago |
| tps1120dr-etched.glb | 1d ago |
| tps1120dr-etched.step | 1d ago |
| tps1120dr-hero.glb | 1d ago |
| tps1120dr-hero.overlay.json | 1d ago |
| tps1120dr.glb | 1d ago |
| tps1120dr.kicad_mod | 1d ago |
| tps1120dr.kicad_sym | 1d ago |
| tps1120dr.lbr | 1d ago |
| tps1120dr.step | 1d ago |
TPS1120DR
Texas Instruments · MOSFETs · SOIC-8
TPS1120DR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1SOURCE | passive | Source terminal of MOSFET 1; the lead is internally tied to the MOSFET 1 source heat sink, and the datasheet gives no separate current limit for this pin. |
| 2 | 1GATE | input | Gate of MOSFET 1; TTL and CMOS compatible input with VGS(th) of -1.5 V maximum. |
| 3 | 2SOURCE | passive | Source terminal of MOSFET 2; the lead is internally tied to the MOSFET 2 source heat sink, and the datasheet gives no separate current limit for this pin. |
| 4 | 2GATE | input | Gate of MOSFET 2; TTL and CMOS compatible input with VGS(th) of -1.5 V maximum. |
| 5 | 2DRAIN | passive | Drain of MOSFET 2; for all applications both drain pins of each device should be connected together. |
| 6 | 2DRAIN | passive | Drain of MOSFET 2; for all applications both drain pins of each device should be connected together. |
| 7 | 1DRAIN | passive | Drain of MOSFET 1; for all applications both drain pins of each device should be connected together. |
| 8 | 1DRAIN | passive | Drain of MOSFET 1; for all applications both drain pins of each device should be connected together. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
TPS1120DR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
tps1120dr-etched.step/tps1120dr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps1120dr.step/tps1120dr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (17 pp, sha256
12ce794c05f16c80, retrieved 2026-10-08, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).