main
Ray Publish 0.1.0 ab6fcff 11d ago
{
  "slug": "tpic6b259dwr",
  "version": "0.1.0",
  "type": "component",
  "description": "Texas Instruments Latches, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "logic",
    "tpic6b259dwr",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "tpic6b259dwr.kicad_sym",
    "tpic6b259dwr.kicad_mod",
    "tpic6b259dwr.glb",
    "tpic6b259dwr.step",
    "tpic6b259dwr.lbr",
    "docs/hero.png",
    "docs/tpic6b259dwr-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "tpic6b259dwr-hero.glb",
    "tpic6b259dwr-hero.overlay.json"
  ],
  "component": {
    "mpn": "TPIC6B259DWR",
    "manufacturer": "Texas Instruments",
    "package": "SOIC-20-300mil",
    "pin_count": 20,
    "category": "Logic",
    "subcategory": "Latches",
    "datasheet": "https://www.ti.com/cn/lit/gpn/tpic6b259",
    "parts": {
      "symbol": "tpic6b259dwr.kicad_sym",
      "footprint": "tpic6b259dwr.kicad_mod",
      "model_3d": "tpic6b259dwr-hero.glb",
      "model_3d_plain": "tpic6b259dwr.glb",
      "model_3d_step": "tpic6b259dwr-etched.step",
      "model_3d_step_plain": "tpic6b259dwr.step",
      "lbr": "tpic6b259dwr.lbr"
    },
    "distributor_links": {
      "lcsc": "C2675347",
      "digikey": "296-TPIC6B259DWRTR-ND",
      "mouser": "595-TPIC6B259DWR"
    },
    "distributor_check": {
      "checked_at": "2026-10-11T09:13:49Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "296-TPIC6B259DWRTR-ND",
        "status": "found",
        "lifecycle": "Active"
      },
      "mouser": {
        "pn": "595-TPIC6B259DWR",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "NC",
        "type": "unconnected",
        "description": "No internal connection."
      },
      {
        "number": "2",
        "name": "VCC",
        "type": "power_in",
        "description": "Logic supply voltage, recommended 4.5 V to 5.5 V (absolute maximum 7 V with respect to GND)."
      },
      {
        "number": "3",
        "name": "S0",
        "type": "input",
        "description": "Latch-select address bit 0 (LSB) that selects which of the eight DMOS outputs is addressed; logic input range is -0.3 V to 7 V."
      },
      {
        "number": "4",
        "name": "DRAIN0",
        "type": "output",
        "description": "Open-drain power DMOS output rated 50 V drain-to-source, 150 mA continuous sink current, with 500 mA typical current limit at TC = 25°C."
      },
      {
        "number": "5",
        "name": "DRAIN1",
        "type": "output",
        "description": "Open-drain power DMOS output rated 50 V drain-to-source, 150 mA continuous sink current, with 500 mA typical current limit at TC = 25°C."
      },
      {
        "number": "6",
        "name": "DRAIN2",
        "type": "output",
        "description": "Open-drain power DMOS output rated 50 V drain-to-source, 150 mA continuous sink current, with 500 mA typical current limit at TC = 25°C."
      },
      {
        "number": "7",
        "name": "DRAIN3",
        "type": "output",
        "description": "Open-drain power DMOS output rated 50 V drain-to-source, 150 mA continuous sink current, with 500 mA typical current limit at TC = 25°C."
      },
      {
        "number": "8",
        "name": "S1",
        "type": "input",
        "description": "Latch-select address bit 1 that selects which of the eight DMOS outputs is addressed; logic input range is -0.3 V to 7 V."
      },
      {
        "number": "9",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference for all voltages; the power DMOS sources are internally connected to GND."
      },
      {
        "number": "10",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference for all voltages; the power DMOS sources are internally connected to GND."
      },
      {
        "number": "11",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference for all voltages; the power DMOS sources are internally connected to GND."
      },
      {
        "number": "12",
        "name": "S2",
        "type": "input",
        "description": "Latch-select address bit 2 (MSB) that selects which of the eight DMOS outputs is addressed; logic input range is -0.3 V to 7 V."
      },
      {
        "number": "13",
        "name": "G",
        "type": "input",
        "description": "Active-low enable; hold high (inactive) while the address lines change to avoid writing erroneous data into the latch."
      },
      {
        "number": "14",
        "name": "DRAIN4",
        "type": "output",
        "description": "Open-drain power DMOS output rated 50 V drain-to-source, 150 mA continuous sink current, with 500 mA typical current limit at TC = 25°C."
      },
      {
        "number": "15",
        "name": "DRAIN5",
        "type": "output",
        "description": "Open-drain power DMOS output rated 50 V drain-to-source, 150 mA continuous sink current, with 500 mA typical current limit at TC = 25°C."
      },
      {
        "number": "16",
        "name": "DRAIN6",
        "type": "output",
        "description": "Open-drain power DMOS output rated 50 V drain-to-source, 150 mA continuous sink current, with 500 mA typical current limit at TC = 25°C."
      },
      {
        "number": "17",
        "name": "DRAIN7",
        "type": "output",
        "description": "Open-drain power DMOS output rated 50 V drain-to-source, 150 mA continuous sink current, with 500 mA typical current limit at TC = 25°C."
      },
      {
        "number": "18",
        "name": "D",
        "type": "input",
        "description": "Data input written into the addressed latch; setup and hold times are 20 ns minimum relative to the rising edge of G."
      },
      {
        "number": "19",
        "name": "CLR",
        "type": "input",
        "description": "Active-low clear; when low, all DMOS outputs are off and unaffected by the address and data inputs."
      },
      {
        "number": "20",
        "name": "NC",
        "type": "unconnected",
        "description": "No internal connection."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The pin-page diagram text is scrambled in extraction, so the right-side pin numbers were inferred fr; Both pins are marked NC (no internal connection) in the datasheet; their positions were inferred fro; Drain outputs are open-drain DMOS sink outputs; the KiCad type 'output' is used since the datasheet "
        ],
        "pages_sent": 20,
        "cost_usd": 0.0821,
        "at": "2026-10-11T09:13:32"
      },
      "datasheet": {
        "url": "https://www.ti.com/cn/lit/gpn/tpic6b259",
        "pages": 20,
        "sha256": "a137e17414bb1cc2",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 20,
        "described": 20,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "tpic6b259dwr.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          10.3,
          12.8,
          2.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "59a10b341e6972b31d81802a048060326da627d8b92dcf4263064f4f62ec808e",
        "checked": "2026-10-11",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "tpic6b259dwr-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          10.3,
          12.8,
          2.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "c88fc1cc977cff2fa5cad45cfd596c85eda3167c8c0569aace4c09d5f1b4e163",
        "checked": "2026-10-11",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}