component

TPIC6B259DWR

Public Made by Adom

by adom

Texas Instruments Latches, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogictpic6b259dwrfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 11d ago
viewers tpic6b259dwr: viewers · Ray 11d ago
package.json Publish 0.1.0 · Ray 11d ago
page.json Set visibility: public · Ray 11d ago
README.md Publish 0.1.0 · Ray 11d ago
tpic6b259dwr-etched.glb tpic6b259dwr: factory component page (tier=lcsc) · Ray 11d ago
tpic6b259dwr-etched.step tpic6b259dwr: factory component page (tier=lcsc) · Ray 11d ago
tpic6b259dwr-hero.glb tpic6b259dwr: hero GLB from the etched model (keeps the MPN mark) · Ray 11d ago
tpic6b259dwr-hero.overlay.json Publish 0.1.0 · Ray 11d ago
tpic6b259dwr.glb Publish 0.1.0 · Ray 11d ago
tpic6b259dwr.kicad_mod Publish 0.1.0 · Ray 11d ago
tpic6b259dwr.kicad_sym Publish 0.1.0 · Ray 11d ago
tpic6b259dwr.lbr Publish 0.1.0 · Ray 11d ago
tpic6b259dwr.step Publish 0.1.0 · Ray 11d ago

TPIC6B259DWR

Texas Instruments · Latches · SOIC-20-300mil

TPIC6B259DWR from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No internal connection.
2 VCC power_in Logic supply voltage, recommended 4.5 V to 5.5 V (absolute maximum 7 V with respect to GND).
3 S0 input Latch-select address bit 0 (LSB) that selects which of the eight DMOS outputs is addressed; logic input range is -0.3 V to 7 V.
4 DRAIN0 output Open-drain power DMOS output rated 50 V drain-to-source, 150 mA continuous sink current, with 500 mA typical current limit at TC = 25°C.
5 DRAIN1 output Open-drain power DMOS output rated 50 V drain-to-source, 150 mA continuous sink current, with 500 mA typical current limit at TC = 25°C.
6 DRAIN2 output Open-drain power DMOS output rated 50 V drain-to-source, 150 mA continuous sink current, with 500 mA typical current limit at TC = 25°C.
7 DRAIN3 output Open-drain power DMOS output rated 50 V drain-to-source, 150 mA continuous sink current, with 500 mA typical current limit at TC = 25°C.
8 S1 input Latch-select address bit 1 that selects which of the eight DMOS outputs is addressed; logic input range is -0.3 V to 7 V.
9 GND power_in Ground reference for all voltages; the power DMOS sources are internally connected to GND.
10 GND power_in Ground reference for all voltages; the power DMOS sources are internally connected to GND.
11 GND power_in Ground reference for all voltages; the power DMOS sources are internally connected to GND.
12 S2 input Latch-select address bit 2 (MSB) that selects which of the eight DMOS outputs is addressed; logic input range is -0.3 V to 7 V.
13 G input Active-low enable; hold high (inactive) while the address lines change to avoid writing erroneous data into the latch.
14 DRAIN4 output Open-drain power DMOS output rated 50 V drain-to-source, 150 mA continuous sink current, with 500 mA typical current limit at TC = 25°C.
15 DRAIN5 output Open-drain power DMOS output rated 50 V drain-to-source, 150 mA continuous sink current, with 500 mA typical current limit at TC = 25°C.
16 DRAIN6 output Open-drain power DMOS output rated 50 V drain-to-source, 150 mA continuous sink current, with 500 mA typical current limit at TC = 25°C.
17 DRAIN7 output Open-drain power DMOS output rated 50 V drain-to-source, 150 mA continuous sink current, with 500 mA typical current limit at TC = 25°C.
18 D input Data input written into the addressed latch; setup and hold times are 20 ns minimum relative to the rising edge of G.
19 CLR input Active-low clear; when low, all DMOS outputs are off and unaffected by the address and data inputs.
20 NC unconnected No internal connection.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-20-300mil
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: TPIC6B259DWR
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
  • 3D model files: tpic6b259dwr-etched.step / tpic6b259dwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tpic6b259dwr.step / tpic6b259dwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (20 pp, sha256 a137e17414bb1cc2, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF