component
TPIC6A596DWRG4
Public Made by Adomby adom
Texas Instruments Shifting Register, SOIC-24-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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{
"slug": "tpic6a596dwrg4",
"version": "0.1.0",
"type": "component",
"description": "Texas Instruments Shifting Register, SOIC-24-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"tags": [
"component",
"logic ics",
"tpic6a596dwrg4",
"factory-2.0.0",
"extractor-text"
],
"dependencies": {},
"hero": {
"type": "image",
"path": "docs/hero.png"
},
"files": [
"page.json",
"README.md",
"tpic6a596dwrg4.kicad_sym",
"tpic6a596dwrg4.kicad_mod",
"tpic6a596dwrg4.glb",
"tpic6a596dwrg4.step",
"tpic6a596dwrg4.lbr",
"docs/hero.png",
"docs/tpic6a596dwrg4-datasheet.pdf",
"viewers/symbol.html",
"viewers/footprint.html",
"tpic6a596dwrg4-hero.glb",
"tpic6a596dwrg4-hero.overlay.json",
"tpic6a596dwrg4-etched.glb"
],
"component": {
"mpn": "TPIC6A596DWRG4",
"manufacturer": "Texas Instruments",
"package": "SOIC-24-300mil",
"pin_count": 24,
"category": "Logic ICs",
"subcategory": "Shifting Register",
"datasheet": "https://www.ti.com/lit/ds/symlink/tpic6a596dwrg4.pdf",
"parts": {
"symbol": "tpic6a596dwrg4.kicad_sym",
"footprint": "tpic6a596dwrg4.kicad_mod",
"model_3d": "tpic6a596dwrg4-hero.glb",
"model_3d_plain": "tpic6a596dwrg4-etched.glb",
"model_3d_step": "tpic6a596dwrg4-etched.step",
"model_3d_step_plain": "tpic6a596dwrg4.step",
"lbr": "tpic6a596dwrg4.lbr"
},
"distributor_links": {
"lcsc": "C2863343",
"digikey": "296-41715-2-ND",
"mouser": "595-TPIC6A596DWRG4"
},
"distributor_check": {
"checked_at": "2026-10-31T00:28:57Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": "296-41715-2-ND",
"status": "found",
"lifecycle": "Discontinued at DigiKey"
},
"mouser": {
"pn": "595-TPIC6A596DWRG4",
"status": "found"
}
},
"pins": [
{
"number": "1",
"name": "DRAIN2",
"type": "output",
"description": "Open-drain DMOS output 2 with 50-V switching capability and 350-mA continuous sink current, with built-in inductive clamp and current limiting."
},
{
"number": "2",
"name": "DRAIN3",
"type": "output",
"description": "Open-drain DMOS output 3 with 50-V switching capability and 350-mA continuous sink current, with built-in inductive clamp and current limiting."
},
{
"number": "3",
"name": "SRCLR",
"type": "input",
"description": "Shift-register clear; when low all registers in the device are cleared, and storage register transfers data to output buffers when high."
},
{
"number": "4",
"name": "G",
"type": "input",
"description": "Output enable; when high all output buffer data is held low and drain outputs are off, when low storage register data is transparent to the output buffers."
},
{
"number": "5",
"name": "PGND",
"type": "power_in",
"description": "Power ground, internally connected to the other PGND pins and must be externally connected to the power system ground."
},
{
"number": "6",
"name": "PGND",
"type": "power_in",
"description": "Power ground, internally connected to the other PGND pins and must be externally connected to the power system ground."
},
{
"number": "7",
"name": "PGND",
"type": "power_in",
"description": "Power ground, internally connected to the other PGND pins and must be externally connected to the power system ground."
},
{
"number": "8",
"name": "PGND",
"type": "power_in",
"description": "Power ground, internally connected to the other PGND pins and must be externally connected to the power system ground."
},
{
"number": "9",
"name": "RCK",
"type": "input",
"description": "Register clock; data transfers from the shift register to the storage register on its rising edge."
},
{
"number": "10",
"name": "SRCK",
"type": "input",
"description": "Shift-register clock; serial data shifts in on the rising edge and SER OUT is clocked out on the falling edge."
},
{
"number": "11",
"name": "DRAIN4",
"type": "output",
"description": "Open-drain DMOS output 4 with 50-V switching capability and 350-mA continuous sink current, with built-in inductive clamp and current limiting."
},
{
"number": "12",
"name": "DRAIN5",
"type": "output",
"description": "Open-drain DMOS output 5 with 50-V switching capability and 350-mA continuous sink current, with built-in inductive clamp and current limiting."
},
{
"number": "13",
"name": "DRAIN6",
"type": "output",
"description": "Open-drain DMOS output 6 with 50-V switching capability and 350-mA continuous sink current, with built-in inductive clamp and current limiting."
},
{
"number": "14",
"name": "DRAIN7",
"type": "output",
"description": "Open-drain DMOS output 7 with 50-V switching capability and 350-mA continuous sink current, with built-in inductive clamp and current limiting."
},
{
"number": "15",
"name": "SER OUT",
"type": "output",
"description": "Serial output of the shift register, clocked out on the falling edge of SRCK for cascading to the next stage."
},
{
"number": "16",
"name": "LGND",
"type": "power_in",
"description": "Logic ground, to be connected at a single point to PGND externally to reduce crosstalk between logic and load circuits."
},
{
"number": "17",
"name": "PGND",
"type": "power_in",
"description": "Power ground, internally connected to the other PGND pins and must be externally connected to the power system ground."
},
{
"number": "18",
"name": "PGND",
"type": "power_in",
"description": "Power ground, internally connected to the other PGND pins and must be externally connected to the power system ground."
},
{
"number": "19",
"name": "PGND",
"type": "power_in",
"description": "Power ground, internally connected to the other PGND pins and must be externally connected to the power system ground."
},
{
"number": "20",
"name": "PGND",
"type": "power_in",
"description": "Power ground, internally connected to the other PGND pins and must be externally connected to the power system ground."
},
{
"number": "21",
"name": "VCC",
"type": "power_in",
"description": "Logic supply voltage, recommended 4.5 V to 5.5 V (absolute maximum 7 V)."
},
{
"number": "22",
"name": "SER IN",
"type": "input",
"description": "Serial data input to the 8-bit shift register, sampled on the rising edge of SRCK."
},
{
"number": "23",
"name": "DRAIN0",
"type": "output",
"description": "Open-drain DMOS output 0 with 50-V switching capability and 350-mA continuous sink current, with built-in inductive clamp and current limiting."
},
{
"number": "24",
"name": "DRAIN1",
"type": "output",
"description": "Open-drain DMOS output 1 with 50-V switching capability and 350-mA continuous sink current, with built-in inductive clamp and current limiting."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: Pin numbers for the DW package were assigned from the order in which the text extraction lists the D; The NE package pin list in the extracted text spells pin 12 as 'DRAN0'; the DW list spells it 'DRAIN; The datasheet gives no separate per-pin electrical limits for the PGND, LGND, or SRCK pins beyond th",
"2/24 pins cited to the wrong page (name found elsewhere): ['1:DRAIN2@p1', '13:DRAIN1@p1']"
],
"pages_sent": 19,
"cost_usd": 0.0933,
"at": "2026-10-31T00:28:39"
},
"datasheet": {
"url": "https://www.ti.com/lit/ds/symlink/tpic6a596dwrg4.pdf",
"pages": 19,
"sha256": "0ecd71440ac33711",
"source_tier": "mfr"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 24,
"described": 24,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"models_3d": [
{
"file": "tpic6a596dwrg4.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
10.3,
15.4,
2.75
],
"zmin_mm": -0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "4b0d20f82f5b0124fecfe11c941274a3c865a30f7baee8b8fadd7df55972d4cd",
"checked": "2026-10-31",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "tpic6a596dwrg4-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
10.3,
15.4,
2.75
],
"zmin_mm": -0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "fc2cb3e874de500b012dd650b3f2ba2aa84ade5fb3a605c37c1b45e2e4b8d704",
"checked": "2026-10-31",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
],
"package_dims": {
"package_code": "DW",
"E1": {
"nom_mm": 7.5,
"range_mm": null
},
"E": {
"nom_mm": 10.3,
"range_mm": null
},
"e": {
"nom_mm": 1.27,
"range_mm": null
},
"source": "TI package designator DW (no drawing in the datasheet)",
"model_check": {
"file": "tpic6a596dwrg4.step",
"verdict": "SKIP",
"reasons": [
"the datasheet dimensions give no height or body size to compare"
],
"by": "factory/package_fit.py"
}
}
}
}