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TPIC6A596DWRG4

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Texas Instruments Shifting Register, SOIC-24-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogic icstpic6a596dwrg4factory-2.0.0extractor-text

Verified TPIC6A596DWRG4

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 24 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: TPIC6A596DWRG4 · SOIC-24-300mil · 24 pins
  • ✓copper: 24 copper pads, none touching another net
  • ✓datasheet: all 24 pin names found in the 19-page datasheet
  • ✓distributor: lcsc C2863343, digikey 296-41715-2-ND, mouser 595-TPIC6A596DWRG4
  • ✓family: SOIC-24W_7.5x15.4mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-yq97qiyv/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): the datasheet dimensions give no height or body size to compare
  • ✓pads: 24 pins = 24 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 24 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ tpic6a596dwrg4.kicad_sym✓ tpic6a596dwrg4.kicad_mod✓ tpic6a596dwrg4.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs Publish 0.1.0 · Ray 10h ago
viewers tpic6a596dwrg4: viewers · Ray 10h ago
package.json Publish 0.1.0 · Ray 10h ago
page.json Set visibility: public · Ray 10h ago
README.md Publish 0.1.0 · Ray 10h ago
tpic6a596dwrg4-etched.glb Publish 0.1.0 · Ray 10h ago
tpic6a596dwrg4-etched.step tpic6a596dwrg4: factory component page (tier=mfr) · Ray 10h ago
tpic6a596dwrg4-hero.glb tpic6a596dwrg4: hero GLB from the etched model (keeps the MPN mark) · Ray 10h ago
tpic6a596dwrg4-hero.overlay.json Publish 0.1.0 · Ray 10h ago
tpic6a596dwrg4.glb Publish 0.1.0 · Ray 10h ago
tpic6a596dwrg4.kicad_mod Publish 0.1.0 · Ray 10h ago
tpic6a596dwrg4.kicad_sym Publish 0.1.0 · Ray 10h ago
tpic6a596dwrg4.lbr Publish 0.1.0 · Ray 10h ago
tpic6a596dwrg4.step Publish 0.1.0 · Ray 10h ago
verification.json Verified: Published by the parts factory: tier mfr, 24 pins · Ray 10h ago

TPIC6A596DWRG4

Texas Instruments · Shifting Register · SOIC-24-300mil

TPIC6A596DWRG4 from Texas Instruments, in a SOIC-24-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DRAIN2 output Open-drain DMOS output 2 with 50-V switching capability and 350-mA continuous sink current, with built-in inductive clamp and current limiting.
2 DRAIN3 output Open-drain DMOS output 3 with 50-V switching capability and 350-mA continuous sink current, with built-in inductive clamp and current limiting.
3 SRCLR input Shift-register clear; when low all registers in the device are cleared, and storage register transfers data to output buffers when high.
4 G input Output enable; when high all output buffer data is held low and drain outputs are off, when low storage register data is transparent to the output buffers.
5 PGND power_in Power ground, internally connected to the other PGND pins and must be externally connected to the power system ground.
6 PGND power_in Power ground, internally connected to the other PGND pins and must be externally connected to the power system ground.
7 PGND power_in Power ground, internally connected to the other PGND pins and must be externally connected to the power system ground.
8 PGND power_in Power ground, internally connected to the other PGND pins and must be externally connected to the power system ground.
9 RCK input Register clock; data transfers from the shift register to the storage register on its rising edge.
10 SRCK input Shift-register clock; serial data shifts in on the rising edge and SER OUT is clocked out on the falling edge.
11 DRAIN4 output Open-drain DMOS output 4 with 50-V switching capability and 350-mA continuous sink current, with built-in inductive clamp and current limiting.
12 DRAIN5 output Open-drain DMOS output 5 with 50-V switching capability and 350-mA continuous sink current, with built-in inductive clamp and current limiting.
13 DRAIN6 output Open-drain DMOS output 6 with 50-V switching capability and 350-mA continuous sink current, with built-in inductive clamp and current limiting.
14 DRAIN7 output Open-drain DMOS output 7 with 50-V switching capability and 350-mA continuous sink current, with built-in inductive clamp and current limiting.
15 SER OUT output Serial output of the shift register, clocked out on the falling edge of SRCK for cascading to the next stage.
16 LGND power_in Logic ground, to be connected at a single point to PGND externally to reduce crosstalk between logic and load circuits.
17 PGND power_in Power ground, internally connected to the other PGND pins and must be externally connected to the power system ground.
18 PGND power_in Power ground, internally connected to the other PGND pins and must be externally connected to the power system ground.
19 PGND power_in Power ground, internally connected to the other PGND pins and must be externally connected to the power system ground.
20 PGND power_in Power ground, internally connected to the other PGND pins and must be externally connected to the power system ground.
21 VCC power_in Logic supply voltage, recommended 4.5 V to 5.5 V (absolute maximum 7 V).
22 SER IN input Serial data input to the 8-bit shift register, sampled on the rising edge of SRCK.
23 DRAIN0 output Open-drain DMOS output 0 with 50-V switching capability and 350-mA continuous sink current, with built-in inductive clamp and current limiting.
24 DRAIN1 output Open-drain DMOS output 1 with 50-V switching capability and 350-mA continuous sink current, with built-in inductive clamp and current limiting.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-24-300mil
Category Logic ICs
Pins 24

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-to-source breakdown voltage V(BR)DSX 50 V ID = 1 mA 5
Source-to-drain diode forward voltage VSD 0.8 1.1 V IF = 350 mA, See Note 3 5
Low-level output voltage VOL 0 0.1 V IOL = 20 µA 5
Low-level output voltage, SER OUT VOL 0.2 0.5 V IOL = 4 mA 5
High-level input current IIH 1 µA VI = VCC 5
Low-level input current IIL -1 µA VI = 0 5
Output current at which chopping starts IO(chop) 0.6 0.8 1.1 A TC = 25°C, See Note 5 and Figures 3 and 4 5
Logic supply current ICC 0.5 5 mA IO = 0, VI = VCC or 0 5
Logic supply current at frequency ICC(FRQ) 1.3 mA fSRCK = 5 MHz, IO = 0, CL = 30 pF, VI = VCC or 0, VCC = 5 V, See Figure 7 5
Nominal current I(nom) 350 mA VDS(on) = 0.5 V, TC = 85°C, VCC = 5 V, See Notes 5, 6, and 7 5
Drain current, off-state ID 0.1 1 µA VDS = 40 V, TC = 25°C 5
Drain current, off-state ID 0.2 5 µA VDS = 40 V, TC = 125°C 5
Static drain-source on-state resistance rDS(on) 1 1.5 Ω ID = 350 mA, TC = 25°C, See Notes 5 and 6 5
Static drain-source on-state resistance rDS(on) 1.7 2.5 Ω ID = 350 mA, TC = 125°C, See Notes 5 and 6 and Figures 10 and 11 5
Propagation delay time, high-to-low-level output from G tPHL 30 ns VCC = 5 V, TC = 25°C 6
Propagation delay time, low-to-high-level output from G tPLH 125 ns VCC = 5 V, TC = 25°C; CL = 30 pF, ID = 350 mA 6
Rise time, drain output tr 60 ns VCC = 5 V, TC = 25°C; CL = 30 pF, ID = 350 mA, See Figures 1, 2, and 12 6
Fall time, drain output tf 30 ns VCC = 5 V, TC = 25°C; CL = 30 pF, ID = 350 mA, See Figures 1, 2, and 12 6
Propagation delay time, SRCK↓ to SEROUT tpd 20 ns VCC = 5 V, TC = 25°C; CL = 30 pF, ID = 350 mA, See Figure 2 6
Serial clock frequency f(SRCK) 10 MHz VCC = 5 V, TC = 25°C; CL = 30 pF, ID = 350 mA, See Note 8 6
Reverse-recovery-current rise time ta 100 ns VCC = 5 V, TC = 25°C; IF = 350 mA, di/dt = 20 A/µs 6
Reverse-recovery time trr 300 ns VCC = 5 V, TC = 25°C; IF = 350 mA, di/dt = 20 A/µs, See Notes 5 and 6 and Figure 5 6
Logic supply voltage VCC 4.5 5.5 V 5
Low-level input voltage VIL 0 V 5
Pulsed drain output current -1.8 0.6 A TC = 25°C, VCC = 5 V, See Notes 3 and 5 5
Setup time, SER IN high before SRCK↑ tsu 10 ns See Figure 2 5
Hold time, SER IN high after SRCK↑ th 10 ns See Figure 2 5
Pulse duration tw 20 ns See Figure 2 5
Operating case temperature TC -40 125 °C 5
Logic supply voltage VCC 7 V See Note 1 4
Logic input voltage range VI -0.3 7 V 4
Power DMOS drain-to-source voltage VDS 50 V See Note 2 4
Continuous source-drain diode anode current 1 A 4
Pulsed source-drain diode anode current 2 A See Note 3 4
Pulsed drain current, each output, all outputs on IDn 1.1 A TA = 25°C, See Note 3 4
Continuous drain current, each output, all outputs on IDn 350 mA TA = 25°C 4
Peak drain current, single output 1.1 A TA = 25°C, See Note 3 4
Single-pulse avalanche energy EAS 75 mJ See Figure 6 4
Avalanche current IAS 600 mA See Note 4 4
Operating case temperature range TC -40 125 °C 4
Operating virtual junction temperature range TJ -40 150 °C 4
Storage temperature range Tstg -65 150 °C 4
Lead temperature 260 °C 1.6 mm (1/16 inch) from case for 10 seconds 4
Continuous total dissipation, DW package, TC ≤ 25°C 1750 mW DW package, TC ≤ 25°C 4
Derating factor above TC = 25°C, DW package 14 mW/°C DW package, above TC = 25°C 4
Power rating at TC = 125°C, DW package 350 mW DW package, TC = 125°C 4
Thermal resistance, junction-to-case, DW RθJC 10 °C/W DW package, all eight outputs with equal power 6
Thermal resistance, junction-to-ambient, DW RθJA 50 °C/W DW package, all eight outputs with equal power 6

CAD (KiCad official)

  • Symbol: TPIC6A596DWRG4
  • Footprint: Package_SO:SOIC-24W_7.5x15.4mm_P1.27mm
  • 3D model: SOIC-24-300mil (KiCad packages3D, STEP)
  • 3D model files: tpic6a596dwrg4-etched.step / tpic6a596dwrg4-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tpic6a596dwrg4.step / tpic6a596dwrg4.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (19 pp, sha256 0ecd71440ac33711, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF