component
TPH1R712MD
Public Made by Adomby adom
TOSHIBA MOSFETs, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TPH1R712MD
TOSHIBA · MOSFETs · SOP-8
TPH1R712MD from TOSHIBA, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source terminal (pins 1, 2 and 3 are all listed as Source); the source connects to the drain-source current path, with DC drain current rated at -60 A and drain-source voltage at -20 V (VDSS). |
| 2 | S | passive | Source terminal (listed with pins 1 and 3 as Source); the source connects to the drain-source current path, with DC drain current rated at -60 A and drain-source voltage at -20 V (VDSS). |
| 3 | S | passive | Source terminal (listed with pins 1 and 2 as Source); the source connects to the drain-source current path, with DC drain current rated at -60 A and drain-source voltage at -20 V (VDSS). |
| 4 | G | input | Gate terminal; the gate-source voltage is limited to ±12 V (VGSS) by the absolute maximum ratings. |
| 5 | Drain | passive | Drain terminal (pins 5 to 8 are all listed as Drain); the drain-source voltage is limited to -20 V (VDSS) and DC drain current to -60 A. |
| 6 | Drain | passive | Drain terminal (pins 5 to 8 are all listed as Drain); the drain-source voltage is limited to -20 V (VDSS) and DC drain current to -60 A. |
| 7 | Drain | passive | Drain terminal (pins 5 to 8 are all listed as Drain); the drain-source voltage is limited to -20 V (VDSS) and DC drain current to -60 A. |
| 8 | Drain | passive | Drain terminal (pins 5 to 8 are all listed as Drain); the drain-source voltage is limited to -20 V (VDSS) and DC drain current to -60 A. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TOSHIBA |
| Package | SOP-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
TPH1R712MD - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
tph1r712md-etched.step/tph1r712md-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tph1r712md.step/tph1r712md.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: TOSHIBA datasheet (9 pp, sha256
d1edc9066862106e, retrieved 2026-10-09, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TPH1R712MD
**TOSHIBA** · MOSFETs · SOP-8
TPH1R712MD from TOSHIBA, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source terminal (pins 1, 2 and 3 are all listed as Source); the source connects to the drain-source current path, with DC drain current rated at -60 A and drain-source voltage at -20 V (VDSS). |
| 2 | S | passive | Source terminal (listed with pins 1 and 3 as Source); the source connects to the drain-source current path, with DC drain current rated at -60 A and drain-source voltage at -20 V (VDSS). |
| 3 | S | passive | Source terminal (listed with pins 1 and 2 as Source); the source connects to the drain-source current path, with DC drain current rated at -60 A and drain-source voltage at -20 V (VDSS). |
| 4 | G | input | Gate terminal; the gate-source voltage is limited to ±12 V (VGSS) by the absolute maximum ratings. |
| 5 | Drain | passive | Drain terminal (pins 5 to 8 are all listed as Drain); the drain-source voltage is limited to -20 V (VDSS) and DC drain current to -60 A. |
| 6 | Drain | passive | Drain terminal (pins 5 to 8 are all listed as Drain); the drain-source voltage is limited to -20 V (VDSS) and DC drain current to -60 A. |
| 7 | Drain | passive | Drain terminal (pins 5 to 8 are all listed as Drain); the drain-source voltage is limited to -20 V (VDSS) and DC drain current to -60 A. |
| 8 | Drain | passive | Drain terminal (pins 5 to 8 are all listed as Drain); the drain-source voltage is limited to -20 V (VDSS) and DC drain current to -60 A. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TOSHIBA |
| Package | SOP-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
## CAD (KiCad official)
- Symbol: `TPH1R712MD`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `tph1r712md-etched.step` / `tph1r712md-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tph1r712md.step` / `tph1r712md.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [TOSHIBA datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588884378453741569) (9 pp, sha256 `d1edc9066862106e`, retrieved 2026-10-09, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tph1r712md-datasheet.pdf)