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Generated by kicad-footprint-generator · KiCad file format 20260206

Name	Last commit message	Last updated
docs	Publish 0.1.0 · Ray	28d ago
viewers	tph1r712md: viewers · Ray	28d ago
package.json	Publish 0.1.0 · Ray	28d ago
page.json	Set visibility: public · Ray	28d ago
README.md	Publish 0.1.0 · Ray	28d ago
tph1r712md-etched.glb	tph1r712md: factory component page (tier=lcsc) · Ray	28d ago
tph1r712md-etched.step	tph1r712md: factory component page (tier=lcsc) · Ray	28d ago
tph1r712md-hero.glb	tph1r712md: hero GLB from the etched model (keeps the MPN mark) · Ray	28d ago
tph1r712md-hero.overlay.json	Publish 0.1.0 · Ray	28d ago
tph1r712md.glb	Publish 0.1.0 · Ray	28d ago
tph1r712md.kicad_mod	Publish 0.1.0 · Ray	28d ago
tph1r712md.kicad_sym	Publish 0.1.0 · Ray	28d ago
tph1r712md.lbr	Publish 0.1.0 · Ray	28d ago
tph1r712md.step	Publish 0.1.0 · Ray	28d ago

TPH1R712MD

TOSHIBA · MOSFETs · SOP-8

TPH1R712MD from TOSHIBA, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	S	passive	Source terminal (pins 1, 2 and 3 are all listed as Source); the source connects to the drain-source current path, with DC drain current rated at -60 A and drain-source voltage at -20 V (VDSS).
2	S	passive	Source terminal (listed with pins 1 and 3 as Source); the source connects to the drain-source current path, with DC drain current rated at -60 A and drain-source voltage at -20 V (VDSS).
3	S	passive	Source terminal (listed with pins 1 and 2 as Source); the source connects to the drain-source current path, with DC drain current rated at -60 A and drain-source voltage at -20 V (VDSS).
4	G	input	Gate terminal; the gate-source voltage is limited to ±12 V (VGSS) by the absolute maximum ratings.
5	Drain	passive	Drain terminal (pins 5 to 8 are all listed as Drain); the drain-source voltage is limited to -20 V (VDSS) and DC drain current to -60 A.
6	Drain	passive	Drain terminal (pins 5 to 8 are all listed as Drain); the drain-source voltage is limited to -20 V (VDSS) and DC drain current to -60 A.
7	Drain	passive	Drain terminal (pins 5 to 8 are all listed as Drain); the drain-source voltage is limited to -20 V (VDSS) and DC drain current to -60 A.
8	Drain	passive	Drain terminal (pins 5 to 8 are all listed as Drain); the drain-source voltage is limited to -20 V (VDSS) and DC drain current to -60 A.

Key specifications

Parameter	Value
Manufacturer	TOSHIBA
Package	SOP-8
Category	Transistors/Thyristors
Pins	8

CAD (KiCad official)

Symbol: TPH1R712MD
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOP-8 (KiCad packages3D, STEP)
3D model files: tph1r712md-etched.step / tph1r712md-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tph1r712md.step / tph1r712md.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: TOSHIBA datasheet (9 pp, sha256 d1edc9066862106e, retrieved 2026-10-09, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF