TMS320VC5502PGF300

{
  "schema_version": 1,
  "type": "component",
  "slug": "tms320vc5502pgf300",
  "title": "TMS320VC5502PGF300",
  "brief": "Texas Instruments Digital Signal Processors (DSP/DSC), LQFP-176(24x24). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "embedded processors & controllers",
    "tms320vc5502pgf300",
    "factory-2.0.0",
    "extractor-text"
  ],
  "component": {
    "mpn": "TMS320VC5502PGF300",
    "manufacturer": "Texas Instruments",
    "package": "LQFP-176(24x24)",
    "pin_count": 176,
    "category": "Embedded Processors & Controllers",
    "subcategory": "Digital Signal Processors (DSP/DSC)",
    "datasheet": "https://www.ti.com/cn/lit/gpn/tms320vc5502",
    "parts": {
      "symbol": "tms320vc5502pgf300.kicad_sym",
      "footprint": "tms320vc5502pgf300.kicad_mod",
      "model_3d": "tms320vc5502pgf300-hero.glb",
      "model_3d_plain": "tms320vc5502pgf300.glb",
      "model_3d_step": "tms320vc5502pgf300-etched.step",
      "model_3d_step_plain": "tms320vc5502pgf300.step",
      "lbr": "tms320vc5502pgf300.lbr"
    },
    "distributor_links": {
      "lcsc": "C882840",
      "digikey": "296-17382-ND",
      "mouser": "595-S320VC5502PGF300"
    },
    "distributor_check": {
      "checked_at": "2026-10-08T21:46:01Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "296-17382-ND",
        "status": "found"
      },
      "mouser": {
        "pn": "595-S320VC5502PGF300",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "GPIO6",
        "type": "bidirectional",
        "description": "Sampled on the rising edge of RESET: low selects HPI non-multiplexed mode and PGPIO/HPI pin functions, high selects EMIF and multiplexed HPI mode."
      },
      {
        "number": "2",
        "name": "GPIO4",
        "type": "bidirectional",
        "description": "Sampled on the rising edge of RESET to set CLKMD0: low selects the internal oscillator with crystal, high selects X2/CLKIN as the input clock."
      },
      {
        "number": "3",
        "name": "GPIO2",
        "type": "bidirectional",
        "description": "Bit-selectable general-purpose I/O pin of the 8-bit GPIO port, configured as input or output through IODIR."
      },
      {
        "number": "4",
        "name": "GPIO1",
        "type": "bidirectional",
        "description": "Bit-selectable general-purpose I/O pin of the 8-bit GPIO port, configured as input or output through IODIR."
      },
      {
        "number": "5",
        "name": "GPIO0",
        "type": "bidirectional",
        "description": "Bit-selectable general-purpose I/O pin (LSB) of the 8-bit GPIO port, configured as input or output through IODIR."
      },
      {
        "number": "6",
        "name": "TIM1",
        "type": "bidirectional",
        "description": "Timer 1 pin configured as timer input (TIN) or output (TOUT) by TIM1_MODE in the TSSR; defaults to input after reset."
      },
      {
        "number": "7",
        "name": "TIM0",
        "type": "bidirectional",
        "description": "Timer 0 pin configured as timer input (TIN) or output (TOUT) by TIM0_MODE in the TSSR; defaults to input after reset."
      },
      {
        "number": "8",
        "name": "INT0",
        "type": "input",
        "description": "External interrupt 0, synchronized to the CPU by a two-flip-flop synchronizer; a low pulse must be at least three CPU clock periods."
      },
      {
        "number": "9",
        "name": "CVDD",
        "type": "power_in",
        "description": "Core VDD supply pin (CVDD is core VDD per the Table 2-3 footnote)."
      },
      {
        "number": "10",
        "name": "INT1",
        "type": "input",
        "description": "External interrupt 1, synchronized to the CPU by a two-flip-flop synchronizer; a low pulse must be at least three CPU clock periods."
      },
      {
        "number": "11",
        "name": "INT2",
        "type": "input",
        "description": "External interrupt 2, synchronized to the CPU by a two-flip-flop synchronizer; a low pulse must be at least three CPU clock periods."
      },
      {
        "number": "12",
        "name": "DVDD",
        "type": "power_in",
        "description": "I/O VDD supply pin (DVDD is I/O VDD per the Table 2-3 footnote)."
      },
      {
        "number": "13",
        "name": "INT3",
        "type": "input",
        "description": "External interrupt 3, which is also the Watchdog timer interrupt input when the WDT interrupt is connected to INT3 through the TSSR."
      },
      {
        "number": "14",
        "name": "NMI/WDTOUT",
        "type": "bidirectional",
        "description": "Configured as NMI input (NMI/WDTOUT_CFG = 1) or Watchdog timer output (= 0); when used as NMI and the WDT is connected to NMI, the external signal is ignored."
      },
      {
        "number": "15",
        "name": "IACK",
        "type": "output",
        "description": "Goes low for one CPU clock pulse when an interrupt vector is fetched, clearing the interrupt flag; it also pulses low to indicate reset deassertion."
      },
      {
        "number": "16",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground pin (VSS)."
      },
      {
        "number": "17",
        "name": "CLKR0",
        "type": "bidirectional",
        "description": "McBSP0 receive clock pin; its pin direction and control are set through the Pin Control Register PCR0."
      },
      {
        "number": "18",
        "name": "DR0",
        "type": "input",
        "description": "McBSP0 serial data receive pin; pin control is set through the Pin Control Register PCR0."
      },
      {
        "number": "19",
        "name": "FSR0",
        "type": "bidirectional",
        "description": "McBSP0 receive frame-synchronization pin; pin control is set through the Pin Control Register PCR0."
      },
      {
        "number": "20",
        "name": "CLKX0",
        "type": "bidirectional",
        "description": "McBSP0 transmit clock pin; pin control is set through the Pin Control Register PCR0."
      },
      {
        "number": "21",
        "name": "CVDD",
        "type": "power_in",
        "description": "Core VDD supply pin (CVDD is core VDD per the Table 2-3 footnote)."
      },
      {
        "number": "22",
        "name": "DX0",
        "type": "output",
        "description": "McBSP0 serial data transmit pin; pin control is set through the Pin Control Register PCR0."
      },
      {
        "number": "23",
        "name": "FSX0",
        "type": "bidirectional",
        "description": "McBSP0 transmit frame-synchronization pin; pin control is set through the Pin Control Register PCR0."
      },
      {
        "number": "24",
        "name": "CLKR1",
        "type": "bidirectional",
        "description": "McBSP1 receive clock pin; pin control is set through the Pin Control Register PCR1."
      },
      {
        "number": "25",
        "name": "DR1",
        "type": "input",
        "description": "McBSP1 serial data receive pin; pin control is set through the Pin Control Register PCR1."
      },
      {
        "number": "26",
        "name": "FSR1",
        "type": "bidirectional",
        "description": "McBSP1 receive frame-synchronization pin; pin control is set through the Pin Control Register PCR1."
      },
      {
        "number": "27",
        "name": "DX1",
        "type": "output",
        "description": "McBSP1 serial data transmit pin; pin control is set through the Pin Control Register PCR1."
      },
      {
        "number": "28",
        "name": "CLKX1",
        "type": "bidirectional",
        "description": "McBSP1 transmit clock pin; pin control is set through the Pin Control Register PCR1."
      },
      {
        "number": "29",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground pin (VSS)."
      },
      {
        "number": "30",
        "name": "FSX1",
        "type": "bidirectional",
        "description": "McBSP1 transmit frame-synchronization pin; pin control is set through the Pin Control Register PCR1."
      },
      {
        "number": "31",
        "name": "DR2",
        "type": "input",
        "description": "McBSP2 serial data receive pin; pin control is set through the Pin Control Register PCR2."
      },
      {
        "number": "32",
        "name": "DX2",
        "type": "output",
        "description": "McBSP2 serial data transmit pin; pin control is set through the Pin Control Register PCR2."
      },
      {
        "number": "33",
        "name": "CVDD",
        "type": "power_in",
        "description": "Core VDD supply pin (CVDD is core VDD per the Table 2-3 footnote)."
      },
      {
        "number": "34",
        "name": "SP3",
        "type": "bidirectional",
        "description": "Serial Port 2 Mux pin; carries the UART RX signal when GPIO7 is low at reset."
      },
      {
        "number": "35",
        "name": "SP2",
        "type": "bidirectional",
        "description": "Serial Port 2 Mux pin; set to GPIO5 when GPIO7 is low at reset and to FSX2 when GPIO7 is high at reset."
      },
      {
        "number": "36",
        "name": "DVDD",
        "type": "power_in",
        "description": "I/O VDD supply pin (DVDD is I/O VDD per the Table 2-3 footnote)."
      },
      {
        "number": "37",
        "name": "SP1",
        "type": "bidirectional",
        "description": "Serial Port 2 Mux pin; carries the UART TX signal when GPIO7 is low at reset."
      },
      {
        "number": "38",
        "name": "SP0",
        "type": "bidirectional",
        "description": "Serial Port 2 Mux pin; set to GPIO3 when GPIO7 is low at reset and to CLKX2 when GPIO7 is high at reset."
      },
      {
        "number": "39",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground pin (VSS)."
      },
      {
        "number": "40",
        "name": "SCL",
        "type": "bidirectional",
        "description": "I2C clock line, a slew-rate limited open-drain output; fast mode is supported up to 400 Kbps with no fail-safe I/O buffers."
      },
      {
        "number": "41",
        "name": "SDA",
        "type": "bidirectional",
        "description": "I2C data line, a slew-rate limited open-drain output with noise filtering for noise of 50 ns or less (I2C module clock 7 to 12 MHz)."
      },
      {
        "number": "42",
        "name": "HC1",
        "type": "bidirectional",
        "description": "HPI control pin, HPI.HBIL in multiplexed mode (GPIO6 high at reset) or PGPIO45 in non-multiplexed mode."
      },
      {
        "number": "43",
        "name": "HC0",
        "type": "bidirectional",
        "description": "HPI control pin, HPI.HAS in multiplexed mode (GPIO6 high at reset) or PGPIO44 in non-multiplexed mode."
      },
      {
        "number": "44",
        "name": "HCS",
        "type": "input",
        "description": "HPI chip select, which must be kept inactive until the internal reset signal has been deasserted (or HPIENA kept low)."
      },
      {
        "number": "45",
        "name": "HCNTL1",
        "type": "input",
        "description": "HPI host control input; its function is defined in the HPI signal table, which is not included in the supplied text."
      },
      {
        "number": "46",
        "name": "HCNTL0",
        "type": "input",
        "description": "HPI host control input; its function is defined in the HPI signal table, which is not included in the supplied text."
      },
      {
        "number": "47",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground pin (VSS)."
      },
      {
        "number": "48",
        "name": "HR/W",
        "type": "input",
        "description": "HPI read/write control input; its function is defined in the HPI signal table, which is not included in the supplied text."
      },
      {
        "number": "49",
        "name": "HDS2",
        "type": "input",
        "description": "HPI data strobe 2, which must be kept inactive until the internal reset signal has been deasserted (or HPIENA kept low)."
      },
      {
        "number": "50",
        "name": "CVDD",
        "type": "power_in",
        "description": "Core VDD supply pin (CVDD is core VDD per the Table 2-3 footnote)."
      },
      {
        "number": "51",
        "name": "HDS1",
        "type": "input",
        "description": "HPI data strobe 1, which must be kept inactive until the internal reset signal has been deasserted (or HPIENA kept low)."
      },
      {
        "number": "52",
        "name": "HRDY",
        "type": "output",
        "description": "HPI ready output used for handshaking with the host."
      },
      {
        "number": "53",
        "name": "DVDD",
        "type": "power_in",
        "description": "I/O VDD supply pin (DVDD is I/O VDD per the Table 2-3 footnote)."
      },
      {
        "number": "54",
        "name": "CLKOUT",
        "type": "output",
        "description": "Clock output whose source is selected by CLKOSEL (SYSCLK1, SYSCLK2 or SYSCLK3) and which drives 0 when CLKOUTDIS is set; it is not placed in high impedance during reset."
      },
      {
        "number": "55",
        "name": "XF",
        "type": "output",
        "description": "External flag output that is not placed in high impedance during reset."
      },
      {
        "number": "56",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground pin (VSS)."
      },
      {
        "number": "57",
        "name": "C15",
        "type": "bidirectional",
        "description": "Parallel port control pin, EMIF.HOLDA when GPIO6 is high at reset or PGPIO35 when GPIO6 is low at reset."
      },
      {
        "number": "58",
        "name": "C14",
        "type": "bidirectional",
        "description": "Parallel port control pin, EMIF.HOLD when GPIO6 is high at reset or PGPIO34 when GPIO6 is low at reset."
      },
      {
        "number": "59",
        "name": "HINT",
        "type": "output",
        "description": "DSP-to-host interrupt output; the HINT bit in the Host Port Control Register (HPIC) should be used for DSP-to-host interrupts."
      },
      {
        "number": "60",
        "name": "PVDD",
        "type": "power_in",
        "description": "PLL VDD supply pin (PVDD is PLL VDD per the Table 2-3 footnote)."
      },
      {
        "number": "61",
        "name": "NC",
        "type": "unconnected",
        "description": "No connect pin (NC)."
      },
      {
        "number": "62",
        "name": "X1",
        "type": "passive",
        "description": "Crystal connection to the internal oscillator; left unconnected when an external clock is applied to X2/CLKIN."
      },
      {
        "number": "63",
        "name": "X2/CLKIN",
        "type": "input",
        "description": "External 3.3-V clock input when GPIO4 is high at reset, or crystal connection when the internal oscillator is used."
      },
      {
        "number": "64",
        "name": "EMIFCLKS",
        "type": "input",
        "description": "Selects the EMIF clock source: low uses the internal clock feeding the data bridge, high uses an external asynchronous clock on ECLKIN of up to 100 MHz."
      },
      {
        "number": "65",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground pin (VSS)."
      },
      {
        "number": "66",
        "name": "C13",
        "type": "bidirectional",
        "description": "Parallel port control pin, EMIF.SOE3 when GPIO6 is high at reset or PGPIO33 when GPIO6 is low at reset."
      },
      {
        "number": "67",
        "name": "C12",
        "type": "bidirectional",
        "description": "Parallel port control pin, EMIF.SDCKE when GPIO6 is high at reset or PGPIO32 when GPIO6 is low at reset."
      },
      {
        "number": "68",
        "name": "C11",
        "type": "bidirectional",
        "description": "Parallel port control pin, EMIF.BE3 when GPIO6 is high at reset or PGPIO31 when GPIO6 is low at reset."
      },
      {
        "number": "69",
        "name": "C10",
        "type": "bidirectional",
        "description": "Parallel port control pin, EMIF.BE2 when GPIO6 is high at reset or PGPIO30 when GPIO6 is low at reset."
      },
      {
        "number": "70",
        "name": "C9",
        "type": "bidirectional",
        "description": "Parallel port control pin, EMIF.BE1 when GPIO6 is high at reset or PGPIO29 when GPIO6 is low at reset."
      },
      {
        "number": "71",
        "name": "C8",
        "type": "bidirectional",
        "description": "Parallel port control pin, EMIF.BE0 when GPIO6 is high at reset or PGPIO28 when GPIO6 is low at reset."
      },
      {
        "number": "72",
        "name": "C7",
        "type": "bidirectional",
        "description": "Parallel port control pin, EMIF.CE3 when GPIO6 is high at reset or PGPIO27 when GPIO6 is low at reset."
      },
      {
        "number": "73",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground pin (VSS)."
      },
      {
        "number": "74",
        "name": "ECLKIN",
        "type": "input",
        "description": "External asynchronous clock input for the EMIF, which must be 100 MHz or less when used."
      },
      {
        "number": "75",
        "name": "ECLKOUT2",
        "type": "output",
        "description": "EMIF clock output 2, which is not placed in high impedance during reset and goes high impedance in HOLD mode only if EK2HZ is set."
      },
      {
        "number": "76",
        "name": "ECLKOUT1",
        "type": "output",
        "description": "EMIF clock output 1, which goes high impedance in HOLD mode only if EK1HZ is set."
      },
      {
        "number": "77",
        "name": "CVDD",
        "type": "power_in",
        "description": "Core VDD supply pin (CVDD is core VDD per the Table 2-3 footnote)."
      },
      {
        "number": "78",
        "name": "C6",
        "type": "bidirectional",
        "description": "Parallel port control pin, EMIF.CE2 when GPIO6 is high at reset or PGPIO26 when GPIO6 is low at reset."
      },
      {
        "number": "79",
        "name": "C5",
        "type": "bidirectional",
        "description": "Parallel port control pin, EMIF.CE1 when GPIO6 is high at reset or PGPIO25 when GPIO6 is low at reset."
      },
      {
        "number": "80",
        "name": "DVDD",
        "type": "power_in",
        "description": "I/O VDD supply pin (DVDD is I/O VDD per the Table 2-3 footnote)."
      },
      {
        "number": "81",
        "name": "C4",
        "type": "bidirectional",
        "description": "Parallel port control pin, EMIF.CE0 when GPIO6 is high at reset or PGPIO24 when GPIO6 is low at reset."
      },
      {
        "number": "82",
        "name": "C3",
        "type": "bidirectional",
        "description": "Parallel port control pin, EMIF.ARDY when GPIO6 is high at reset or PGPIO23 when GPIO6 is low at reset."
      },
      {
        "number": "83",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground pin (VSS)."
      },
      {
        "number": "84",
        "name": "C2",
        "type": "bidirectional",
        "description": "Parallel port control pin, EMIF.AWE/SWE/SDWE when GPIO6 is high at reset or PGPIO22 when GPIO6 is low at reset."
      },
      {
        "number": "85",
        "name": "C1",
        "type": "bidirectional",
        "description": "Parallel port control pin, EMIF.AOE/SOE/SDRAS when GPIO6 is high at reset or PGPIO21 when GPIO6 is low at reset."
      },
      {
        "number": "86",
        "name": "C0",
        "type": "bidirectional",
        "description": "Parallel port control pin, PGPIO20 when GPIO6 is low at reset or EMIF.ARE/SADS/SDCAS/SRE when GPIO6 is high at reset."
      },
      {
        "number": "87",
        "name": "A21",
        "type": "bidirectional",
        "description": "Parallel port address pin, EMIF.A21 when GPIO6 is high at reset or part of the PGPIO[3:0] group when GPIO6 is low; bus holder enabled at reset."
      },
      {
        "number": "88",
        "name": "A20",
        "type": "bidirectional",
        "description": "Parallel port address pin, EMIF.A20 when GPIO6 is high at reset or part of the PGPIO[3:0] group when GPIO6 is low; bus holder enabled at reset."
      },
      {
        "number": "89",
        "name": "A19",
        "type": "bidirectional",
        "description": "Parallel port address pin, EMIF.A19 when GPIO6 is high at reset or part of the PGPIO[3:0] group when GPIO6 is low; bus holder enabled at reset."
      },
      {
        "number": "90",
        "name": "A18",
        "type": "bidirectional",
        "description": "Parallel port address pin, EMIF.A18 when GPIO6 is high at reset or part of the PGPIO[3:0] group when GPIO6 is low; bus holder enabled at reset."
      },
      {
        "number": "91",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground pin (VSS)."
      },
      {
        "number": "92",
        "name": "A17",
        "type": "bidirectional",
        "description": "Parallel port address pin, EMIF.A17 when GPIO6 is high at reset or HPI.HA[15:0] when GPIO6 is low; bus holder enabled at reset."
      },
      {
        "number": "93",
        "name": "A16",
        "type": "bidirectional",
        "description": "Parallel port address pin, EMIF.A16 when GPIO6 is high at reset or HPI.HA[15:0] when GPIO6 is low; bus holder enabled at reset."
      },
      {
        "number": "94",
        "name": "DVDD",
        "type": "power_in",
        "description": "I/O VDD supply pin (DVDD is I/O VDD per the Table 2-3 footnote)."
      },
      {
        "number": "95",
        "name": "A15",
        "type": "bidirectional",
        "description": "Parallel port address pin, EMIF.A15 when GPIO6 is high at reset or HPI.HA[15:0] when GPIO6 is low; bus holder enabled at reset."
      },
      {
        "number": "96",
        "name": "A14",
        "type": "bidirectional",
        "description": "Parallel port address pin, EMIF.A14 when GPIO6 is high at reset or HPI.HA[15:0] when GPIO6 is low; bus holder enabled at reset."
      },
      {
        "number": "97",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground pin (VSS)."
      },
      {
        "number": "98",
        "name": "A13",
        "type": "bidirectional",
        "description": "Parallel port address pin, EMIF.A13 when GPIO6 is high at reset or HPI.HA[15:0] when GPIO6 is low; bus holder enabled at reset."
      },
      {
        "number": "99",
        "name": "A12",
        "type": "bidirectional",
        "description": "Parallel port address pin, EMIF.A12 when GPIO6 is high at reset or HPI.HA[15:0] when GPIO6 is low; bus holder enabled at reset."
      },
      {
        "number": "100",
        "name": "CVDD",
        "type": "power_in",
        "description": "Core VDD supply pin (CVDD is core VDD per the Table 2-3 footnote)."
      },
      {
        "number": "101",
        "name": "A11",
        "type": "bidirectional",
        "description": "Parallel port address pin, EMIF.A11 when GPIO6 is high at reset or HPI.HA[15:0] when GPIO6 is low; bus holder enabled at reset."
      },
      {
        "number": "102",
        "name": "A10",
        "type": "bidirectional",
        "description": "Parallel port address pin, EMIF.A10 when GPIO6 is high at reset or HPI.HA[15:0] when GPIO6 is low; bus holder enabled at reset."
      },
      {
        "number": "103",
        "name": "A9",
        "type": "bidirectional",
        "description": "Parallel port address pin, EMIF.A9 when GPIO6 is high at reset or HPI.HA[15:0] when GPIO6 is low; bus holder enabled at reset."
      },
      {
        "number": "104",
        "name": "A8",
        "type": "bidirectional",
        "description": "Parallel port address pin, EMIF.A8 when GPIO6 is high at reset or HPI.HA[15:0] when GPIO6 is low; bus holder enabled at reset."
      },
      {
        "number": "105",
        "name": "DVDD",
        "type": "power_in",
        "description": "I/O VDD supply pin (DVDD is I/O VDD per the Table 2-3 footnote)."
      },
      {
        "number": "106",
        "name": "A7",
        "type": "bidirectional",
        "description": "Parallel port address pin, EMIF.A7 when GPIO6 is high at reset or HPI.HA[15:0] when GPIO6 is low; bus holder enabled at reset."
      },
      {
        "number": "107",
        "name": "A6",
        "type": "bidirectional",
        "description": "Parallel port address pin, EMIF.A6 when GPIO6 is high at reset or HPI.HA[15:0] when GPIO6 is low; bus holder enabled at reset."
      },
      {
        "number": "108",
        "name": "A5",
        "type": "bidirectional",
        "description": "Parallel port address pin, EMIF.A5 when GPIO6 is high at reset or HPI.HA[15:0] when GPIO6 is low; bus holder enabled at reset."
      },
      {
        "number": "109",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground pin (VSS)."
      },
      {
        "number": "110",
        "name": "A4",
        "type": "bidirectional",
        "description": "Parallel port address pin, EMIF.A4 when GPIO6 is high at reset or HPI.HA[15:0] when GPIO6 is low; bus holder enabled at reset."
      },
      {
        "number": "111",
        "name": "A3",
        "type": "bidirectional",
        "description": "Parallel port address pin, EMIF.A3 when GPIO6 is high at reset or HPI.HA[15:0] when GPIO6 is low; bus holder enabled at reset."
      },
      {
        "number": "112",
        "name": "A2",
        "type": "bidirectional",
        "description": "Parallel port address pin, EMIF.A2 when GPIO6 is high at reset or HPI.HA[15:0] when GPIO6 is low; bus holder enabled at reset."
      },
      {
        "number": "113",
        "name": "CVDD",
        "type": "power_in",
        "description": "Core VDD supply pin (CVDD is core VDD per the Table 2-3 footnote)."
      },
      {
        "number": "114",
        "name": "D31",
        "type": "bidirectional",
        "description": "Parallel port data pin, EMIF.D31 when GPIO6 is high at reset or PGPIO19 when GPIO6 is low; bus holder enabled at reset."
      },
      {
        "number": "115",
        "name": "D30",
        "type": "bidirectional",
        "description": "Parallel port data pin, EMIF.D30 when GPIO6 is high at reset or part of PGPIO[19:4] when GPIO6 is low; bus holder enabled at reset."
      },
      {
        "number": "116",
        "name": "D29",
        "type": "bidirectional",
        "description": "Parallel port data pin, EMIF.D29 when GPIO6 is high at reset or part of PGPIO[19:4] when GPIO6 is low; bus holder enabled at reset."
      },
      {
        "number": "117",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground pin (VSS)."
      },
      {
        "number": "118",
        "name": "D28",
        "type": "bidirectional",
        "description": "Parallel port data pin, EMIF.D28 when GPIO6 is high at reset or part of PGPIO[19:4] when GPIO6 is low; bus holder enabled at reset."
      },
      {
        "number": "119",
        "name": "D27",
        "type": "bidirectional",
        "description": "Parallel port data pin, EMIF.D27 when GPIO6 is high at reset or part of PGPIO[19:4] when GPIO6 is low; bus holder enabled at reset."
      },
      {
        "number": "120",
        "name": "D26",
        "type": "bidirectional",
        "description": "Parallel port data pin, EMIF.D26 when GPIO6 is high at reset or part of PGPIO[19:4] when GPIO6 is low; bus holder enabled at reset."
      },
      {
        "number": "121",
        "name": "CVDD",
        "type": "power_in",
        "description": "Core VDD supply pin (CVDD is core VDD per the Table 2-3 footnote)."
      },
      {
        "number": "122",
        "name": "D25",
        "type": "bidirectional",
        "description": "Parallel port data pin, EMIF.D25 when GPIO6 is high at reset or part of PGPIO[19:4] when GPIO6 is low; bus holder enabled at reset."
      },
      {
        "number": "123",
        "name": "D24",
        "type": "bidirectional",
        "description": "Parallel port data pin, EMIF.D24 when GPIO6 is high at reset or part of PGPIO[19:4] when GPIO6 is low; bus holder enabled at reset."
      },
      {
        "number": "124",
        "name": "DVDD",
        "type": "power_in",
        "description": "I/O VDD supply pin (DVDD is I/O VDD per the Table 2-3 footnote)."
      },
      {
        "number": "125",
        "name": "D23",
        "type": "bidirectional",
        "description": "Parallel port data pin, EMIF.D23 when GPIO6 is high at reset or part of PGPIO[19:4] when GPIO6 is low; bus holder enabled at reset."
      },
      {
        "number": "126",
        "name": "D22",
        "type": "bidirectional",
        "description": "Parallel port data pin, EMIF.D22 when GPIO6 is high at reset or part of PGPIO[19:4] when GPIO6 is low; bus holder enabled at reset."
      },
      {
        "number": "127",
        "name": "D21",
        "type": "bidirectional",
        "description": "Parallel port data pin, EMIF.D21 when GPIO6 is high at reset or part of PGPIO[19:4] when GPIO6 is low; bus holder enabled at reset."
      },
      {
        "number": "128",
        "name": "D20",
        "type": "bidirectional",
        "description": "Parallel port data pin, EMIF.D20 when GPIO6 is high at reset or part of PGPIO[19:4] when GPIO6 is low; bus holder enabled at reset."
      },
      {
        "number": "129",
        "name": "D19",
        "type": "bidirectional",
        "description": "Parallel port data pin, EMIF.D19 when GPIO6 is high at reset or part of PGPIO[19:4] when GPIO6 is low; bus holder enabled at reset."
      },
      {
        "number": "130",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground pin (VSS)."
      },
      {
        "number": "131",
        "name": "D18",
        "type": "bidirectional",
        "description": "Parallel port data pin, EMIF.D18 when GPIO6 is high at reset or part of PGPIO[19:4] when GPIO6 is low; bus holder enabled at reset."
      },
      {
        "number": "132",
        "name": "D17",
        "type": "bidirectional",
        "description": "Parallel port data pin, EMIF.D17 when GPIO6 is high at reset or part of PGPIO[19:4] when GPIO6 is low; bus holder enabled at reset."
      },
      {
        "number": "133",
        "name": "D16",
        "type": "bidirectional",
        "description": "Parallel port data pin, EMIF.D16 when GPIO6 is high at reset or part of PGPIO[19:4] when GPIO6 is low; bus holder enabled at reset."
      },
      {
        "number": "134",
        "name": "D15",
        "type": "bidirectional",
        "description": "Parallel port data pin, HPI.HD15 when GPIO6 is low at reset or EMIF.D15 when GPIO6 is high; bus holder enabled at reset."
      },
      {
        "number": "135",
        "name": "D14",
        "type": "bidirectional",
        "description": "Parallel port data pin, HPI.HD14 when GPIO6 is low at reset or EMIF.D14 when GPIO6 is high; bus holder enabled at reset."
      },
      {
        "number": "136",
        "name": "D13",
        "type": "bidirectional",
        "description": "Parallel port data pin, HPI.HD13 when GPIO6 is low at reset or EMIF.D13 when GPIO6 is high; bus holder enabled at reset."
      },
      {
        "number": "137",
        "name": "D12",
        "type": "bidirectional",
        "description": "Parallel port data pin, HPI.HD12 when GPIO6 is low at reset or EMIF.D12 when GPIO6 is high; bus holder enabled at reset."
      },
      {
        "number": "138",
        "name": "D11",
        "type": "bidirectional",
        "description": "Parallel port data pin, HPI.HD11 when GPIO6 is low at reset or EMIF.D11 when GPIO6 is high; bus holder enabled at reset."
      },
      {
        "number": "139",
        "name": "D10",
        "type": "bidirectional",
        "description": "Parallel port data pin, HPI.HD10 when GPIO6 is low at reset or EMIF.D10 when GPIO6 is high; bus holder enabled at reset."
      },
      {
        "number": "140",
        "name": "D9",
        "type": "bidirectional",
        "description": "Parallel port data pin, HPI.HD9 when GPIO6 is low at reset or EMIF.D9 when GPIO6 is high; bus holder enabled at reset."
      },
      {
        "number": "141",
        "name": "DVDD",
        "type": "power_in",
        "description": "I/O VDD supply pin (DVDD is I/O VDD per the Table 2-3 footnote)."
      },
      {
        "number": "142",
        "name": "D8",
        "type": "bidirectional",
        "description": "Parallel port data pin, HPI.HD8 when GPIO6 is low at reset or EMIF.D8 when GPIO6 is high; bus holder enabled at reset."
      },
      {
        "number": "143",
        "name": "D7",
        "type": "bidirectional",
        "description": "Parallel port data pin, HPI.HD7 when GPIO6 is low at reset or EMIF.D7 when GPIO6 is high; bus holder enabled at reset."
      },
      {
        "number": "144",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground pin (VSS)."
      },
      {
        "number": "145",
        "name": "D6",
        "type": "bidirectional",
        "description": "Parallel port data pin, HPI.HD6 when GPIO6 is low at reset or EMIF.D6 when GPIO6 is high; bus holder enabled at reset."
      },
      {
        "number": "146",
        "name": "D5",
        "type": "bidirectional",
        "description": "Parallel port data pin, HPI.HD5 when GPIO6 is low at reset or EMIF.D5 when GPIO6 is high; bus holder enabled at reset."
      },
      {
        "number": "147",
        "name": "D4",
        "type": "bidirectional",
        "description": "Parallel port data pin, HPI.HD4 when GPIO6 is low at reset or EMIF.D4 when GPIO6 is high; bus holder enabled at reset."
      },
      {
        "number": "148",
        "name": "CVDD",
        "type": "power_in",
        "description": "Core VDD supply pin (CVDD is core VDD per the Table 2-3 footnote)."
      },
      {
        "number": "149",
        "name": "D3",
        "type": "bidirectional",
        "description": "Parallel port data pin, HPI.HD3 when GPIO6 is low at reset or EMIF.D3 when GPIO6 is high; bus holder enabled at reset."
      },
      {
        "number": "150",
        "name": "D2",
        "type": "bidirectional",
        "description": "Parallel port data pin, HPI.HD2 when GPIO6 is low at reset or EMIF.D2 when GPIO6 is high; bus holder enabled at reset."
      },
      {
        "number": "151",
        "name": "D1",
        "type": "bidirectional",
        "description": "Parallel port data pin, HPI.HD1 when GPIO6 is low at reset or EMIF.D1 when GPIO6 is high; bus holder enabled at reset."
      },
      {
        "number": "152",
        "name": "D0",
        "type": "bidirectional",
        "description": "Parallel port data pin, HPI.HD0 when GPIO6 is low at reset or EMIF.D0 when GPIO6 is high; bus holder enabled at reset."
      },
      {
        "number": "153",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground pin (VSS)."
      },
      {
        "number": "154",
        "name": "EMU1/OFF",
        "type": "bidirectional",
        "description": "Emulation pin with internal pullup; the pin is high impedance in OFF mode when TRST = 0, EMU0 = 1 and EMU1/OFF = 0."
      },
      {
        "number": "155",
        "name": "EMU0",
        "type": "bidirectional",
        "description": "Emulation pin with internal pullup; it must be held high through a rising edge of TRST for boundary scan test."
      },
      {
        "number": "156",
        "name": "TDO",
        "type": "output",
        "description": "JTAG test data output, used with the boundary scan and emulation interface described in Section 4.1."
      },
      {
        "number": "157",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground pin (VSS)."
      },
      {
        "number": "158",
        "name": "TDI",
        "type": "input",
        "description": "JTAG test data input with internal pullup."
      },
      {
        "number": "159",
        "name": "TRST",
        "type": "input",
        "description": "JTAG test reset input with internal pulldown; a rising edge of TRST with EMU0 or EMU1/OFF not high may select a factory test mode."
      },
      {
        "number": "160",
        "name": "TCK",
        "type": "input",
        "description": "JTAG test clock input with internal pullup; TCK transitions must be faster than 3 ns with clean monotonic edges to avoid erroneous clock edges."
      },
      {
        "number": "161",
        "name": "TMS",
        "type": "input",
        "description": "JTAG test mode select input with internal pullup."
      },
      {
        "number": "162",
        "name": "RESET",
        "type": "input",
        "description": "Reset input; while low, output and I/O pins are high impedance, and GPIO4, GPIO6 and GPIO7 are sampled on its rising edge."
      },
      {
        "number": "163",
        "name": "HPIENA",
        "type": "input",
        "description": "HPI enable input; keep it low until the internal reset signal has been deasserted, or keep HCS, HDS1 and HDS2 inactive instead."
      },
      {
        "number": "164",
        "name": "HD7",
        "type": "bidirectional",
        "description": "Host port data pin, HPI.HD7 in multiplexed 8-bit mode (GPIO6 high at reset) or PGPIO43 in non-multiplexed mode; bus holder enabled at reset."
      },
      {
        "number": "165",
        "name": "CVDD",
        "type": "power_in",
        "description": "Core VDD supply pin (CVDD is core VDD per the Table 2-3 footnote)."
      },
      {
        "number": "166",
        "name": "HD6",
        "type": "bidirectional",
        "description": "Host port data pin, HPI.HD6 in multiplexed 8-bit mode (GPIO6 high at reset) or PGPIO42 in non-multiplexed mode; bus holder enabled at reset."
      },
      {
        "number": "167",
        "name": "HD5",
        "type": "bidirectional",
        "description": "Host port data pin, HPI.HD5 in multiplexed 8-bit mode (GPIO6 high at reset) or PGPIO41 in non-multiplexed mode; bus holder enabled at reset."
      },
      {
        "number": "168",
        "name": "DVDD",
        "type": "power_in",
        "description": "I/O VDD supply pin (DVDD is I/O VDD per the Table 2-3 footnote)."
      },
      {
        "number": "169",
        "name": "HD4",
        "type": "bidirectional",
        "description": "Host port data pin, HPI.HD4 in multiplexed 8-bit mode (GPIO6 high at reset) or PGPIO40 in non-multiplexed mode; bus holder enabled at reset."
      },
      {
        "number": "170",
        "name": "HD3",
        "type": "bidirectional",
        "description": "Host port data pin, HPI.HD3 in multiplexed 8-bit mode (GPIO6 high at reset) or PGPIO39 in non-multiplexed mode; bus holder enabled at reset."
      },
      {
        "number": "171",
        "name": "CVDD",
        "type": "power_in",
        "description": "Core VDD supply pin (CVDD is core VDD per the Table 2-3 footnote)."
      },
      {
        "number": "172",
        "name": "HD2",
        "type": "bidirectional",
        "description": "Host port data pin, HPI.HD2 in multiplexed 8-bit mode (GPIO6 high at reset) or PGPIO38 in non-multiplexed mode; bus holder enabled at reset."
      },
      {
        "number": "173",
        "name": "HD1",
        "type": "bidirectional",
        "description": "Host port data pin, HPI.HD1 in multiplexed 8-bit mode (GPIO6 high at reset) or PGPIO37 in non-multiplexed mode; bus holder enabled at reset."
      },
      {
        "number": "174",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground pin (VSS)."
      },
      {
        "number": "175",
        "name": "HD0",
        "type": "bidirectional",
        "description": "Host port data pin, HPI.HD0 in multiplexed 8-bit mode (GPIO6 high at reset) or PGPIO36 in non-multiplexed mode; bus holder enabled at reset."
      },
      {
        "number": "176",
        "name": "GPIO7",
        "type": "bidirectional",
        "description": "Sampled on the rising edge of RESET to select the Serial Port 2 Mux mode: low enables the UART, high disables it; it also selects SP0/SP2 as GPIO3/GPIO5 or CLKX2/FSX2."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The 176-pin PGF pin table (Table 2-3, page 20) is used for all pin numbers and names. Figure 2-2 is ; Power pin voltage limits (CVDD, DVDD, PVDD) and the ground definition are not stated in the supplied; Table 2-4 signal descriptions for HPI host control and strobe pins beyond page 22 were not in the su",
          "60/176 pins cited to the wrong page (name found elsewhere): ['14:NMI/WDTOUT@p48', '17:CLKR0@p116', '18:DR0@p116', '19:FSR0@p116']"
        ],
        "pages_sent": 99,
        "cost_usd": 0.7671,
        "at": "2026-10-08T21:45:14"
      },
      "datasheet": {
        "url": "https://www.ti.com/cn/lit/gpn/tms320vc5502",
        "pages": 199,
        "sha256": "f888c20bc65aafd4",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 176,
        "described": 176,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "tms320vc5502pgf300.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          26,
          26,
          1.5
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "af405b3ced8ef09a67c3c4732e526f53f88a9b9f83ce7d10b8fa299331f6842a",
        "checked": "2026-10-08",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "tms320vc5502pgf300-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          26,
          26,
          1.5
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "c77618d7290fb2f9eed2e1ec28577f6071d6ac3e6263361b5dcace296ccdf391",
        "checked": "2026-10-08",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "Texas Instruments",
      "Package": "LQFP-176(24x24)",
      "Category": "Embedded Processors & Controllers",
      "Pins": "176"
    }
  },
  "variants": [],
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "tms320vc5502pgf300"
  ],
  "discovery_pitch": "TMS320VC5502PGF300 (Texas Instruments) component page: datasheet pinout, KiCad symbol, footprint and 3D.",
  "author": {
    "name": "Ray",
    "email": "[email protected]"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "tms320vc5502pgf300.kicad_sym",
    "tms320vc5502pgf300.kicad_mod",
    "tms320vc5502pgf300.glb",
    "tms320vc5502pgf300.step",
    "tms320vc5502pgf300.lbr",
    "docs/hero.png",
    "docs/tms320vc5502pgf300-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "tms320vc5502pgf300-hero.glb",
    "tms320vc5502pgf300-hero.overlay.json"
  ],
  "visibility": {
    "public": true
  }
}