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TMS320VC5502PGF300

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Texas Instruments Digital Signal Processors (DSP/DSC), LQFP-176(24x24). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TMS320VC5502PGF300

Texas Instruments · Digital Signal Processors (DSP/DSC) · LQFP-176(24x24)

TMS320VC5502PGF300 from Texas Instruments, in a LQFP-176(24x24). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GPIO6 bidirectional Sampled on the rising edge of RESET: low selects HPI non-multiplexed mode and PGPIO/HPI pin functions, high selects EMIF and multiplexed HPI mode.
2 GPIO4 bidirectional Sampled on the rising edge of RESET to set CLKMD0: low selects the internal oscillator with crystal, high selects X2/CLKIN as the input clock.
3 GPIO2 bidirectional Bit-selectable general-purpose I/O pin of the 8-bit GPIO port, configured as input or output through IODIR.
4 GPIO1 bidirectional Bit-selectable general-purpose I/O pin of the 8-bit GPIO port, configured as input or output through IODIR.
5 GPIO0 bidirectional Bit-selectable general-purpose I/O pin (LSB) of the 8-bit GPIO port, configured as input or output through IODIR.
6 TIM1 bidirectional Timer 1 pin configured as timer input (TIN) or output (TOUT) by TIM1_MODE in the TSSR; defaults to input after reset.
7 TIM0 bidirectional Timer 0 pin configured as timer input (TIN) or output (TOUT) by TIM0_MODE in the TSSR; defaults to input after reset.
8 INT0 input External interrupt 0, synchronized to the CPU by a two-flip-flop synchronizer; a low pulse must be at least three CPU clock periods.
9 CVDD power_in Core VDD supply pin (CVDD is core VDD per the Table 2-3 footnote).
10 INT1 input External interrupt 1, synchronized to the CPU by a two-flip-flop synchronizer; a low pulse must be at least three CPU clock periods.
11 INT2 input External interrupt 2, synchronized to the CPU by a two-flip-flop synchronizer; a low pulse must be at least three CPU clock periods.
12 DVDD power_in I/O VDD supply pin (DVDD is I/O VDD per the Table 2-3 footnote).
13 INT3 input External interrupt 3, which is also the Watchdog timer interrupt input when the WDT interrupt is connected to INT3 through the TSSR.
14 NMI/WDTOUT bidirectional Configured as NMI input (NMI/WDTOUT_CFG = 1) or Watchdog timer output (= 0); when used as NMI and the WDT is connected to NMI, the external signal is ignored.
15 IACK output Goes low for one CPU clock pulse when an interrupt vector is fetched, clearing the interrupt flag; it also pulses low to indicate reset deassertion.
16 VSS power_in Ground pin (VSS).
17 CLKR0 bidirectional McBSP0 receive clock pin; its pin direction and control are set through the Pin Control Register PCR0.
18 DR0 input McBSP0 serial data receive pin; pin control is set through the Pin Control Register PCR0.
19 FSR0 bidirectional McBSP0 receive frame-synchronization pin; pin control is set through the Pin Control Register PCR0.
20 CLKX0 bidirectional McBSP0 transmit clock pin; pin control is set through the Pin Control Register PCR0.
21 CVDD power_in Core VDD supply pin (CVDD is core VDD per the Table 2-3 footnote).
22 DX0 output McBSP0 serial data transmit pin; pin control is set through the Pin Control Register PCR0.
23 FSX0 bidirectional McBSP0 transmit frame-synchronization pin; pin control is set through the Pin Control Register PCR0.
24 CLKR1 bidirectional McBSP1 receive clock pin; pin control is set through the Pin Control Register PCR1.
25 DR1 input McBSP1 serial data receive pin; pin control is set through the Pin Control Register PCR1.
26 FSR1 bidirectional McBSP1 receive frame-synchronization pin; pin control is set through the Pin Control Register PCR1.
27 DX1 output McBSP1 serial data transmit pin; pin control is set through the Pin Control Register PCR1.
28 CLKX1 bidirectional McBSP1 transmit clock pin; pin control is set through the Pin Control Register PCR1.
29 VSS power_in Ground pin (VSS).
30 FSX1 bidirectional McBSP1 transmit frame-synchronization pin; pin control is set through the Pin Control Register PCR1.
31 DR2 input McBSP2 serial data receive pin; pin control is set through the Pin Control Register PCR2.
32 DX2 output McBSP2 serial data transmit pin; pin control is set through the Pin Control Register PCR2.
33 CVDD power_in Core VDD supply pin (CVDD is core VDD per the Table 2-3 footnote).
34 SP3 bidirectional Serial Port 2 Mux pin; carries the UART RX signal when GPIO7 is low at reset.
35 SP2 bidirectional Serial Port 2 Mux pin; set to GPIO5 when GPIO7 is low at reset and to FSX2 when GPIO7 is high at reset.
36 DVDD power_in I/O VDD supply pin (DVDD is I/O VDD per the Table 2-3 footnote).
37 SP1 bidirectional Serial Port 2 Mux pin; carries the UART TX signal when GPIO7 is low at reset.
38 SP0 bidirectional Serial Port 2 Mux pin; set to GPIO3 when GPIO7 is low at reset and to CLKX2 when GPIO7 is high at reset.
39 VSS power_in Ground pin (VSS).
40 SCL bidirectional I2C clock line, a slew-rate limited open-drain output; fast mode is supported up to 400 Kbps with no fail-safe I/O buffers.
41 SDA bidirectional I2C data line, a slew-rate limited open-drain output with noise filtering for noise of 50 ns or less (I2C module clock 7 to 12 MHz).
42 HC1 bidirectional HPI control pin, HPI.HBIL in multiplexed mode (GPIO6 high at reset) or PGPIO45 in non-multiplexed mode.
43 HC0 bidirectional HPI control pin, HPI.HAS in multiplexed mode (GPIO6 high at reset) or PGPIO44 in non-multiplexed mode.
44 HCS input HPI chip select, which must be kept inactive until the internal reset signal has been deasserted (or HPIENA kept low).
45 HCNTL1 input HPI host control input; its function is defined in the HPI signal table, which is not included in the supplied text.
46 HCNTL0 input HPI host control input; its function is defined in the HPI signal table, which is not included in the supplied text.
47 VSS power_in Ground pin (VSS).
48 HR/W input HPI read/write control input; its function is defined in the HPI signal table, which is not included in the supplied text.
49 HDS2 input HPI data strobe 2, which must be kept inactive until the internal reset signal has been deasserted (or HPIENA kept low).
50 CVDD power_in Core VDD supply pin (CVDD is core VDD per the Table 2-3 footnote).
51 HDS1 input HPI data strobe 1, which must be kept inactive until the internal reset signal has been deasserted (or HPIENA kept low).
52 HRDY output HPI ready output used for handshaking with the host.
53 DVDD power_in I/O VDD supply pin (DVDD is I/O VDD per the Table 2-3 footnote).
54 CLKOUT output Clock output whose source is selected by CLKOSEL (SYSCLK1, SYSCLK2 or SYSCLK3) and which drives 0 when CLKOUTDIS is set; it is not placed in high impedance during reset.
55 XF output External flag output that is not placed in high impedance during reset.
56 VSS power_in Ground pin (VSS).
57 C15 bidirectional Parallel port control pin, EMIF.HOLDA when GPIO6 is high at reset or PGPIO35 when GPIO6 is low at reset.
58 C14 bidirectional Parallel port control pin, EMIF.HOLD when GPIO6 is high at reset or PGPIO34 when GPIO6 is low at reset.
59 HINT output DSP-to-host interrupt output; the HINT bit in the Host Port Control Register (HPIC) should be used for DSP-to-host interrupts.
60 PVDD power_in PLL VDD supply pin (PVDD is PLL VDD per the Table 2-3 footnote).
61 NC unconnected No connect pin (NC).
62 X1 passive Crystal connection to the internal oscillator; left unconnected when an external clock is applied to X2/CLKIN.
63 X2/CLKIN input External 3.3-V clock input when GPIO4 is high at reset, or crystal connection when the internal oscillator is used.
64 EMIFCLKS input Selects the EMIF clock source: low uses the internal clock feeding the data bridge, high uses an external asynchronous clock on ECLKIN of up to 100 MHz.
65 VSS power_in Ground pin (VSS).
66 C13 bidirectional Parallel port control pin, EMIF.SOE3 when GPIO6 is high at reset or PGPIO33 when GPIO6 is low at reset.
67 C12 bidirectional Parallel port control pin, EMIF.SDCKE when GPIO6 is high at reset or PGPIO32 when GPIO6 is low at reset.
68 C11 bidirectional Parallel port control pin, EMIF.BE3 when GPIO6 is high at reset or PGPIO31 when GPIO6 is low at reset.
69 C10 bidirectional Parallel port control pin, EMIF.BE2 when GPIO6 is high at reset or PGPIO30 when GPIO6 is low at reset.
70 C9 bidirectional Parallel port control pin, EMIF.BE1 when GPIO6 is high at reset or PGPIO29 when GPIO6 is low at reset.
71 C8 bidirectional Parallel port control pin, EMIF.BE0 when GPIO6 is high at reset or PGPIO28 when GPIO6 is low at reset.
72 C7 bidirectional Parallel port control pin, EMIF.CE3 when GPIO6 is high at reset or PGPIO27 when GPIO6 is low at reset.
73 VSS power_in Ground pin (VSS).
74 ECLKIN input External asynchronous clock input for the EMIF, which must be 100 MHz or less when used.
75 ECLKOUT2 output EMIF clock output 2, which is not placed in high impedance during reset and goes high impedance in HOLD mode only if EK2HZ is set.
76 ECLKOUT1 output EMIF clock output 1, which goes high impedance in HOLD mode only if EK1HZ is set.
77 CVDD power_in Core VDD supply pin (CVDD is core VDD per the Table 2-3 footnote).
78 C6 bidirectional Parallel port control pin, EMIF.CE2 when GPIO6 is high at reset or PGPIO26 when GPIO6 is low at reset.
79 C5 bidirectional Parallel port control pin, EMIF.CE1 when GPIO6 is high at reset or PGPIO25 when GPIO6 is low at reset.
80 DVDD power_in I/O VDD supply pin (DVDD is I/O VDD per the Table 2-3 footnote).
81 C4 bidirectional Parallel port control pin, EMIF.CE0 when GPIO6 is high at reset or PGPIO24 when GPIO6 is low at reset.
82 C3 bidirectional Parallel port control pin, EMIF.ARDY when GPIO6 is high at reset or PGPIO23 when GPIO6 is low at reset.
83 VSS power_in Ground pin (VSS).
84 C2 bidirectional Parallel port control pin, EMIF.AWE/SWE/SDWE when GPIO6 is high at reset or PGPIO22 when GPIO6 is low at reset.
85 C1 bidirectional Parallel port control pin, EMIF.AOE/SOE/SDRAS when GPIO6 is high at reset or PGPIO21 when GPIO6 is low at reset.
86 C0 bidirectional Parallel port control pin, PGPIO20 when GPIO6 is low at reset or EMIF.ARE/SADS/SDCAS/SRE when GPIO6 is high at reset.
87 A21 bidirectional Parallel port address pin, EMIF.A21 when GPIO6 is high at reset or part of the PGPIO[3:0] group when GPIO6 is low; bus holder enabled at reset.
88 A20 bidirectional Parallel port address pin, EMIF.A20 when GPIO6 is high at reset or part of the PGPIO[3:0] group when GPIO6 is low; bus holder enabled at reset.
89 A19 bidirectional Parallel port address pin, EMIF.A19 when GPIO6 is high at reset or part of the PGPIO[3:0] group when GPIO6 is low; bus holder enabled at reset.
90 A18 bidirectional Parallel port address pin, EMIF.A18 when GPIO6 is high at reset or part of the PGPIO[3:0] group when GPIO6 is low; bus holder enabled at reset.
91 VSS power_in Ground pin (VSS).
92 A17 bidirectional Parallel port address pin, EMIF.A17 when GPIO6 is high at reset or HPI.HA[15:0] when GPIO6 is low; bus holder enabled at reset.
93 A16 bidirectional Parallel port address pin, EMIF.A16 when GPIO6 is high at reset or HPI.HA[15:0] when GPIO6 is low; bus holder enabled at reset.
94 DVDD power_in I/O VDD supply pin (DVDD is I/O VDD per the Table 2-3 footnote).
95 A15 bidirectional Parallel port address pin, EMIF.A15 when GPIO6 is high at reset or HPI.HA[15:0] when GPIO6 is low; bus holder enabled at reset.
96 A14 bidirectional Parallel port address pin, EMIF.A14 when GPIO6 is high at reset or HPI.HA[15:0] when GPIO6 is low; bus holder enabled at reset.
97 VSS power_in Ground pin (VSS).
98 A13 bidirectional Parallel port address pin, EMIF.A13 when GPIO6 is high at reset or HPI.HA[15:0] when GPIO6 is low; bus holder enabled at reset.
99 A12 bidirectional Parallel port address pin, EMIF.A12 when GPIO6 is high at reset or HPI.HA[15:0] when GPIO6 is low; bus holder enabled at reset.
100 CVDD power_in Core VDD supply pin (CVDD is core VDD per the Table 2-3 footnote).
101 A11 bidirectional Parallel port address pin, EMIF.A11 when GPIO6 is high at reset or HPI.HA[15:0] when GPIO6 is low; bus holder enabled at reset.
102 A10 bidirectional Parallel port address pin, EMIF.A10 when GPIO6 is high at reset or HPI.HA[15:0] when GPIO6 is low; bus holder enabled at reset.
103 A9 bidirectional Parallel port address pin, EMIF.A9 when GPIO6 is high at reset or HPI.HA[15:0] when GPIO6 is low; bus holder enabled at reset.
104 A8 bidirectional Parallel port address pin, EMIF.A8 when GPIO6 is high at reset or HPI.HA[15:0] when GPIO6 is low; bus holder enabled at reset.
105 DVDD power_in I/O VDD supply pin (DVDD is I/O VDD per the Table 2-3 footnote).
106 A7 bidirectional Parallel port address pin, EMIF.A7 when GPIO6 is high at reset or HPI.HA[15:0] when GPIO6 is low; bus holder enabled at reset.
107 A6 bidirectional Parallel port address pin, EMIF.A6 when GPIO6 is high at reset or HPI.HA[15:0] when GPIO6 is low; bus holder enabled at reset.
108 A5 bidirectional Parallel port address pin, EMIF.A5 when GPIO6 is high at reset or HPI.HA[15:0] when GPIO6 is low; bus holder enabled at reset.
109 VSS power_in Ground pin (VSS).
110 A4 bidirectional Parallel port address pin, EMIF.A4 when GPIO6 is high at reset or HPI.HA[15:0] when GPIO6 is low; bus holder enabled at reset.
111 A3 bidirectional Parallel port address pin, EMIF.A3 when GPIO6 is high at reset or HPI.HA[15:0] when GPIO6 is low; bus holder enabled at reset.
112 A2 bidirectional Parallel port address pin, EMIF.A2 when GPIO6 is high at reset or HPI.HA[15:0] when GPIO6 is low; bus holder enabled at reset.
113 CVDD power_in Core VDD supply pin (CVDD is core VDD per the Table 2-3 footnote).
114 D31 bidirectional Parallel port data pin, EMIF.D31 when GPIO6 is high at reset or PGPIO19 when GPIO6 is low; bus holder enabled at reset.
115 D30 bidirectional Parallel port data pin, EMIF.D30 when GPIO6 is high at reset or part of PGPIO[19:4] when GPIO6 is low; bus holder enabled at reset.
116 D29 bidirectional Parallel port data pin, EMIF.D29 when GPIO6 is high at reset or part of PGPIO[19:4] when GPIO6 is low; bus holder enabled at reset.
117 VSS power_in Ground pin (VSS).
118 D28 bidirectional Parallel port data pin, EMIF.D28 when GPIO6 is high at reset or part of PGPIO[19:4] when GPIO6 is low; bus holder enabled at reset.
119 D27 bidirectional Parallel port data pin, EMIF.D27 when GPIO6 is high at reset or part of PGPIO[19:4] when GPIO6 is low; bus holder enabled at reset.
120 D26 bidirectional Parallel port data pin, EMIF.D26 when GPIO6 is high at reset or part of PGPIO[19:4] when GPIO6 is low; bus holder enabled at reset.
121 CVDD power_in Core VDD supply pin (CVDD is core VDD per the Table 2-3 footnote).
122 D25 bidirectional Parallel port data pin, EMIF.D25 when GPIO6 is high at reset or part of PGPIO[19:4] when GPIO6 is low; bus holder enabled at reset.
123 D24 bidirectional Parallel port data pin, EMIF.D24 when GPIO6 is high at reset or part of PGPIO[19:4] when GPIO6 is low; bus holder enabled at reset.
124 DVDD power_in I/O VDD supply pin (DVDD is I/O VDD per the Table 2-3 footnote).
125 D23 bidirectional Parallel port data pin, EMIF.D23 when GPIO6 is high at reset or part of PGPIO[19:4] when GPIO6 is low; bus holder enabled at reset.
126 D22 bidirectional Parallel port data pin, EMIF.D22 when GPIO6 is high at reset or part of PGPIO[19:4] when GPIO6 is low; bus holder enabled at reset.
127 D21 bidirectional Parallel port data pin, EMIF.D21 when GPIO6 is high at reset or part of PGPIO[19:4] when GPIO6 is low; bus holder enabled at reset.
128 D20 bidirectional Parallel port data pin, EMIF.D20 when GPIO6 is high at reset or part of PGPIO[19:4] when GPIO6 is low; bus holder enabled at reset.
129 D19 bidirectional Parallel port data pin, EMIF.D19 when GPIO6 is high at reset or part of PGPIO[19:4] when GPIO6 is low; bus holder enabled at reset.
130 VSS power_in Ground pin (VSS).
131 D18 bidirectional Parallel port data pin, EMIF.D18 when GPIO6 is high at reset or part of PGPIO[19:4] when GPIO6 is low; bus holder enabled at reset.
132 D17 bidirectional Parallel port data pin, EMIF.D17 when GPIO6 is high at reset or part of PGPIO[19:4] when GPIO6 is low; bus holder enabled at reset.
133 D16 bidirectional Parallel port data pin, EMIF.D16 when GPIO6 is high at reset or part of PGPIO[19:4] when GPIO6 is low; bus holder enabled at reset.
134 D15 bidirectional Parallel port data pin, HPI.HD15 when GPIO6 is low at reset or EMIF.D15 when GPIO6 is high; bus holder enabled at reset.
135 D14 bidirectional Parallel port data pin, HPI.HD14 when GPIO6 is low at reset or EMIF.D14 when GPIO6 is high; bus holder enabled at reset.
136 D13 bidirectional Parallel port data pin, HPI.HD13 when GPIO6 is low at reset or EMIF.D13 when GPIO6 is high; bus holder enabled at reset.
137 D12 bidirectional Parallel port data pin, HPI.HD12 when GPIO6 is low at reset or EMIF.D12 when GPIO6 is high; bus holder enabled at reset.
138 D11 bidirectional Parallel port data pin, HPI.HD11 when GPIO6 is low at reset or EMIF.D11 when GPIO6 is high; bus holder enabled at reset.
139 D10 bidirectional Parallel port data pin, HPI.HD10 when GPIO6 is low at reset or EMIF.D10 when GPIO6 is high; bus holder enabled at reset.
140 D9 bidirectional Parallel port data pin, HPI.HD9 when GPIO6 is low at reset or EMIF.D9 when GPIO6 is high; bus holder enabled at reset.
141 DVDD power_in I/O VDD supply pin (DVDD is I/O VDD per the Table 2-3 footnote).
142 D8 bidirectional Parallel port data pin, HPI.HD8 when GPIO6 is low at reset or EMIF.D8 when GPIO6 is high; bus holder enabled at reset.
143 D7 bidirectional Parallel port data pin, HPI.HD7 when GPIO6 is low at reset or EMIF.D7 when GPIO6 is high; bus holder enabled at reset.
144 VSS power_in Ground pin (VSS).
145 D6 bidirectional Parallel port data pin, HPI.HD6 when GPIO6 is low at reset or EMIF.D6 when GPIO6 is high; bus holder enabled at reset.
146 D5 bidirectional Parallel port data pin, HPI.HD5 when GPIO6 is low at reset or EMIF.D5 when GPIO6 is high; bus holder enabled at reset.
147 D4 bidirectional Parallel port data pin, HPI.HD4 when GPIO6 is low at reset or EMIF.D4 when GPIO6 is high; bus holder enabled at reset.
148 CVDD power_in Core VDD supply pin (CVDD is core VDD per the Table 2-3 footnote).
149 D3 bidirectional Parallel port data pin, HPI.HD3 when GPIO6 is low at reset or EMIF.D3 when GPIO6 is high; bus holder enabled at reset.
150 D2 bidirectional Parallel port data pin, HPI.HD2 when GPIO6 is low at reset or EMIF.D2 when GPIO6 is high; bus holder enabled at reset.
151 D1 bidirectional Parallel port data pin, HPI.HD1 when GPIO6 is low at reset or EMIF.D1 when GPIO6 is high; bus holder enabled at reset.
152 D0 bidirectional Parallel port data pin, HPI.HD0 when GPIO6 is low at reset or EMIF.D0 when GPIO6 is high; bus holder enabled at reset.
153 VSS power_in Ground pin (VSS).
154 EMU1/OFF bidirectional Emulation pin with internal pullup; the pin is high impedance in OFF mode when TRST = 0, EMU0 = 1 and EMU1/OFF = 0.
155 EMU0 bidirectional Emulation pin with internal pullup; it must be held high through a rising edge of TRST for boundary scan test.
156 TDO output JTAG test data output, used with the boundary scan and emulation interface described in Section 4.1.
157 VSS power_in Ground pin (VSS).
158 TDI input JTAG test data input with internal pullup.
159 TRST input JTAG test reset input with internal pulldown; a rising edge of TRST with EMU0 or EMU1/OFF not high may select a factory test mode.
160 TCK input JTAG test clock input with internal pullup; TCK transitions must be faster than 3 ns with clean monotonic edges to avoid erroneous clock edges.
161 TMS input JTAG test mode select input with internal pullup.
162 RESET input Reset input; while low, output and I/O pins are high impedance, and GPIO4, GPIO6 and GPIO7 are sampled on its rising edge.
163 HPIENA input HPI enable input; keep it low until the internal reset signal has been deasserted, or keep HCS, HDS1 and HDS2 inactive instead.
164 HD7 bidirectional Host port data pin, HPI.HD7 in multiplexed 8-bit mode (GPIO6 high at reset) or PGPIO43 in non-multiplexed mode; bus holder enabled at reset.
165 CVDD power_in Core VDD supply pin (CVDD is core VDD per the Table 2-3 footnote).
166 HD6 bidirectional Host port data pin, HPI.HD6 in multiplexed 8-bit mode (GPIO6 high at reset) or PGPIO42 in non-multiplexed mode; bus holder enabled at reset.
167 HD5 bidirectional Host port data pin, HPI.HD5 in multiplexed 8-bit mode (GPIO6 high at reset) or PGPIO41 in non-multiplexed mode; bus holder enabled at reset.
168 DVDD power_in I/O VDD supply pin (DVDD is I/O VDD per the Table 2-3 footnote).
169 HD4 bidirectional Host port data pin, HPI.HD4 in multiplexed 8-bit mode (GPIO6 high at reset) or PGPIO40 in non-multiplexed mode; bus holder enabled at reset.
170 HD3 bidirectional Host port data pin, HPI.HD3 in multiplexed 8-bit mode (GPIO6 high at reset) or PGPIO39 in non-multiplexed mode; bus holder enabled at reset.
171 CVDD power_in Core VDD supply pin (CVDD is core VDD per the Table 2-3 footnote).
172 HD2 bidirectional Host port data pin, HPI.HD2 in multiplexed 8-bit mode (GPIO6 high at reset) or PGPIO38 in non-multiplexed mode; bus holder enabled at reset.
173 HD1 bidirectional Host port data pin, HPI.HD1 in multiplexed 8-bit mode (GPIO6 high at reset) or PGPIO37 in non-multiplexed mode; bus holder enabled at reset.
174 VSS power_in Ground pin (VSS).
175 HD0 bidirectional Host port data pin, HPI.HD0 in multiplexed 8-bit mode (GPIO6 high at reset) or PGPIO36 in non-multiplexed mode; bus holder enabled at reset.
176 GPIO7 bidirectional Sampled on the rising edge of RESET to select the Serial Port 2 Mux mode: low enables the UART, high disables it; it also selects SP0/SP2 as GPIO3/GPIO5 or CLKX2/FSX2.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-176(24x24)
Category Embedded Processors & Controllers
Pins 176

CAD (KiCad official)

  • Symbol: TMS320VC5502PGF300
  • Footprint: Package_QFP:LQFP-176_24x24mm_P0.5mm
  • 3D model: LQFP-176(24x24) (KiCad packages3D, STEP)
  • 3D model files: tms320vc5502pgf300-etched.step / tms320vc5502pgf300-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tms320vc5502pgf300.step / tms320vc5502pgf300.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (199 pp, sha256 f888c20bc65aafd4, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF