TMS320VC33PGE150

{
  "schema_version": 1,
  "type": "component",
  "slug": "tms320vc33pge150",
  "title": "TMS320VC33PGE150",
  "brief": "Texas Instruments Digital Signal Processors (DSP/DSC), LQFP-144(20x20). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "embedded processors & controllers",
    "tms320vc33pge150",
    "factory-2.0.0",
    "extractor-text"
  ],
  "component": {
    "mpn": "TMS320VC33PGE150",
    "manufacturer": "Texas Instruments",
    "package": "LQFP-144(20x20)",
    "pin_count": 144,
    "category": "Embedded Processors & Controllers",
    "subcategory": "Digital Signal Processors (DSP/DSC)",
    "datasheet": "https://www.ti.com/cn/lit/gpn/tms320vc33",
    "parts": {
      "symbol": "tms320vc33pge150.kicad_sym",
      "footprint": "tms320vc33pge150.kicad_mod",
      "model_3d": "tms320vc33pge150-hero.glb",
      "model_3d_plain": "tms320vc33pge150.glb",
      "model_3d_step": "tms320vc33pge150-etched.step",
      "model_3d_step_plain": "tms320vc33pge150.step",
      "lbr": "tms320vc33pge150.lbr"
    },
    "distributor_links": {
      "lcsc": "C701558",
      "digikey": "296-12166-ND",
      "mouser": "595-TMS320VC33PGE150"
    },
    "distributor_check": {
      "checked_at": "2026-10-08T02:52:29Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "296-12166-ND",
        "status": "found",
        "lifecycle": "Not For New Designs"
      },
      "mouser": {
        "pn": "595-TMS320VC33PGE150",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "A20",
        "type": "tri_state",
        "description": "24-bit primary-bus address output bit A20; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "2",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane."
      },
      {
        "number": "3",
        "name": "A19",
        "type": "tri_state",
        "description": "24-bit primary-bus address output bit A19; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "4",
        "name": "A18",
        "type": "tri_state",
        "description": "24-bit primary-bus address output bit A18; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "5",
        "name": "A17",
        "type": "tri_state",
        "description": "24-bit primary-bus address output bit A17; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "6",
        "name": "DVDD",
        "type": "power_in",
        "description": "Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling)."
      },
      {
        "number": "7",
        "name": "A16",
        "type": "tri_state",
        "description": "24-bit primary-bus address output bit A16; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "8",
        "name": "A15",
        "type": "tri_state",
        "description": "24-bit primary-bus address output bit A15; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "9",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane."
      },
      {
        "number": "10",
        "name": "A14",
        "type": "tri_state",
        "description": "24-bit primary-bus address output bit A14; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "11",
        "name": "A13",
        "type": "tri_state",
        "description": "24-bit primary-bus address output bit A13; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "12",
        "name": "CVDD",
        "type": "power_in",
        "description": "Dedicated 1.8-V supply for the core CPU; all CVDD pins must be connected to a common supply plane (four 0.1 µF recommended decoupling)."
      },
      {
        "number": "13",
        "name": "A12",
        "type": "tri_state",
        "description": "24-bit primary-bus address output bit A12; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "14",
        "name": "A11",
        "type": "tri_state",
        "description": "24-bit primary-bus address output bit A11; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "15",
        "name": "DVDD",
        "type": "power_in",
        "description": "Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling)."
      },
      {
        "number": "16",
        "name": "A10",
        "type": "tri_state",
        "description": "24-bit primary-bus address output bit A10; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "17",
        "name": "A9",
        "type": "tri_state",
        "description": "24-bit primary-bus address output bit A9; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "18",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane."
      },
      {
        "number": "19",
        "name": "A8",
        "type": "tri_state",
        "description": "24-bit primary-bus address output bit A8; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "20",
        "name": "A7",
        "type": "tri_state",
        "description": "24-bit primary-bus address output bit A7; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "21",
        "name": "A6",
        "type": "tri_state",
        "description": "24-bit primary-bus address output bit A6; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "22",
        "name": "A5",
        "type": "tri_state",
        "description": "24-bit primary-bus address output bit A5; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "23",
        "name": "DVDD",
        "type": "power_in",
        "description": "Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling)."
      },
      {
        "number": "24",
        "name": "A4",
        "type": "tri_state",
        "description": "24-bit primary-bus address output bit A4; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "25",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane."
      },
      {
        "number": "26",
        "name": "A3",
        "type": "tri_state",
        "description": "24-bit primary-bus address output bit A3; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "27",
        "name": "A2",
        "type": "tri_state",
        "description": "24-bit primary-bus address output bit A2; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "28",
        "name": "CVDD",
        "type": "power_in",
        "description": "Dedicated 1.8-V supply for the core CPU; all CVDD pins must be connected to a common supply plane (four 0.1 µF recommended decoupling)."
      },
      {
        "number": "29",
        "name": "A1",
        "type": "tri_state",
        "description": "24-bit primary-bus address output bit A1; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "30",
        "name": "A0",
        "type": "tri_state",
        "description": "24-bit primary-bus address output bit A0; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "31",
        "name": "DVDD",
        "type": "power_in",
        "description": "Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling)."
      },
      {
        "number": "32",
        "name": "PAGE3",
        "type": "tri_state",
        "description": "Decoded page strobe 3 for external access; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "33",
        "name": "PAGE2",
        "type": "tri_state",
        "description": "Decoded page strobe 2 for external access; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "34",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane."
      },
      {
        "number": "35",
        "name": "PAGE1",
        "type": "tri_state",
        "description": "Decoded page strobe 1 for external access; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "36",
        "name": "PAGE0",
        "type": "tri_state",
        "description": "Decoded page strobe 0 for external access; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "37",
        "name": "DVDD",
        "type": "power_in",
        "description": "Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling)."
      },
      {
        "number": "38",
        "name": "H1",
        "type": "tri_state",
        "description": "External H1 clock output; high-impedance when SHZ is active."
      },
      {
        "number": "39",
        "name": "H3",
        "type": "tri_state",
        "description": "External H3 clock output; high-impedance when SHZ is active."
      },
      {
        "number": "40",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane."
      },
      {
        "number": "41",
        "name": "STRB",
        "type": "tri_state",
        "description": "Strobe output for all external accesses; high-impedance when SHZ or HOLD is active."
      },
      {
        "number": "42",
        "name": "R/W",
        "type": "tri_state",
        "description": "Read/write output: high for a read and low for a write over the parallel interface; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "43",
        "name": "DVDD",
        "type": "power_in",
        "description": "Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling)."
      },
      {
        "number": "44",
        "name": "IACK",
        "type": "tri_state",
        "description": "Interrupt acknowledge output generated by the IACK instruction, which can indicate when a section of code is executing; high-impedance when SHZ is active."
      },
      {
        "number": "45",
        "name": "RDY",
        "type": "input",
        "description": "Ready input indicating that the external device is prepared for transaction completion."
      },
      {
        "number": "46",
        "name": "CVDD",
        "type": "power_in",
        "description": "Dedicated 1.8-V supply for the core CPU; all CVDD pins must be connected to a common supply plane (four 0.1 µF recommended decoupling)."
      },
      {
        "number": "47",
        "name": "HOLD",
        "type": "input",
        "description": "Hold input: when low, the ongoing transaction completes and the address, data, STRB and R/W outputs go high-impedance until HOLD returns high or the NOHOLD bit is set."
      },
      {
        "number": "48",
        "name": "HOLDA",
        "type": "tri_state",
        "description": "Hold acknowledge output asserted in response to a logic-low on HOLD, indicating the primary bus is high-impedance and transactions are held; high-impedance when SHZ is active."
      },
      {
        "number": "49",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane."
      },
      {
        "number": "50",
        "name": "D31",
        "type": "bidirectional",
        "description": "Primary-bus 32-bit data port bit D31 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "51",
        "name": "D30",
        "type": "bidirectional",
        "description": "Primary-bus 32-bit data port bit D30 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "52",
        "name": "D29",
        "type": "bidirectional",
        "description": "Primary-bus 32-bit data port bit D29 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "53",
        "name": "DVDD",
        "type": "power_in",
        "description": "Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling)."
      },
      {
        "number": "54",
        "name": "D28",
        "type": "bidirectional",
        "description": "Primary-bus 32-bit data port bit D28 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "55",
        "name": "D27",
        "type": "bidirectional",
        "description": "Primary-bus 32-bit data port bit D27 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "56",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane."
      },
      {
        "number": "57",
        "name": "D26",
        "type": "bidirectional",
        "description": "Primary-bus 32-bit data port bit D26 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "58",
        "name": "D25",
        "type": "bidirectional",
        "description": "Primary-bus 32-bit data port bit D25 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "59",
        "name": "D24",
        "type": "bidirectional",
        "description": "Primary-bus 32-bit data port bit D24 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "60",
        "name": "DVDD",
        "type": "power_in",
        "description": "Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling)."
      },
      {
        "number": "61",
        "name": "D23",
        "type": "bidirectional",
        "description": "Primary-bus 32-bit data port bit D23 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "62",
        "name": "D22",
        "type": "bidirectional",
        "description": "Primary-bus 32-bit data port bit D22 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "63",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane."
      },
      {
        "number": "64",
        "name": "D21",
        "type": "bidirectional",
        "description": "Primary-bus 32-bit data port bit D21 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "65",
        "name": "D20",
        "type": "bidirectional",
        "description": "Primary-bus 32-bit data port bit D20 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "66",
        "name": "CVDD",
        "type": "power_in",
        "description": "Dedicated 1.8-V supply for the core CPU; all CVDD pins must be connected to a common supply plane (four 0.1 µF recommended decoupling)."
      },
      {
        "number": "67",
        "name": "D19",
        "type": "bidirectional",
        "description": "Primary-bus 32-bit data port bit D19 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "68",
        "name": "D18",
        "type": "bidirectional",
        "description": "Primary-bus 32-bit data port bit D18 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "69",
        "name": "DVDD",
        "type": "power_in",
        "description": "Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling)."
      },
      {
        "number": "70",
        "name": "D17",
        "type": "bidirectional",
        "description": "Primary-bus 32-bit data port bit D17 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "71",
        "name": "D16",
        "type": "bidirectional",
        "description": "Primary-bus 32-bit data port bit D16 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "72",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane."
      },
      {
        "number": "73",
        "name": "D15",
        "type": "bidirectional",
        "description": "Primary-bus 32-bit data port bit D15 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "74",
        "name": "D14",
        "type": "bidirectional",
        "description": "Primary-bus 32-bit data port bit D14 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "75",
        "name": "D13",
        "type": "bidirectional",
        "description": "Primary-bus 32-bit data port bit D13 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "76",
        "name": "D12",
        "type": "bidirectional",
        "description": "Primary-bus 32-bit data port bit D12 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "77",
        "name": "DVDD",
        "type": "power_in",
        "description": "Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling)."
      },
      {
        "number": "78",
        "name": "D11",
        "type": "bidirectional",
        "description": "Primary-bus 32-bit data port bit D11 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "79",
        "name": "D10",
        "type": "bidirectional",
        "description": "Primary-bus 32-bit data port bit D10 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "80",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane."
      },
      {
        "number": "81",
        "name": "D9",
        "type": "bidirectional",
        "description": "Primary-bus 32-bit data port bit D9 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "82",
        "name": "D8",
        "type": "bidirectional",
        "description": "Primary-bus 32-bit data port bit D8 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "83",
        "name": "CVDD",
        "type": "power_in",
        "description": "Dedicated 1.8-V supply for the core CPU; all CVDD pins must be connected to a common supply plane (four 0.1 µF recommended decoupling)."
      },
      {
        "number": "84",
        "name": "D7",
        "type": "bidirectional",
        "description": "Primary-bus 32-bit data port bit D7 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "85",
        "name": "D6",
        "type": "bidirectional",
        "description": "Primary-bus 32-bit data port bit D6 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "86",
        "name": "DVDD",
        "type": "power_in",
        "description": "Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling)."
      },
      {
        "number": "87",
        "name": "D5",
        "type": "bidirectional",
        "description": "Primary-bus 32-bit data port bit D5 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "88",
        "name": "D4",
        "type": "bidirectional",
        "description": "Primary-bus 32-bit data port bit D4 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "89",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane."
      },
      {
        "number": "90",
        "name": "D3",
        "type": "bidirectional",
        "description": "Primary-bus 32-bit data port bit D3 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "91",
        "name": "D2",
        "type": "bidirectional",
        "description": "Primary-bus 32-bit data port bit D2 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "92",
        "name": "D1",
        "type": "bidirectional",
        "description": "Primary-bus 32-bit data port bit D1 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "93",
        "name": "D0",
        "type": "bidirectional",
        "description": "Primary-bus 32-bit data port bit D0 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "94",
        "name": "DVDD",
        "type": "power_in",
        "description": "Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling)."
      },
      {
        "number": "95",
        "name": "EMU1",
        "type": "bidirectional",
        "description": "JTAG emulation pin 1; use an individual pullup to DVDD."
      },
      {
        "number": "96",
        "name": "EMU0",
        "type": "bidirectional",
        "description": "JTAG emulation pin 0; use an individual pullup to DVDD."
      },
      {
        "number": "97",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane."
      },
      {
        "number": "98",
        "name": "TCK",
        "type": "input",
        "description": "JTAG test clock input; has an internal pullup."
      },
      {
        "number": "99",
        "name": "TDO",
        "type": "output",
        "description": "JTAG test data output."
      },
      {
        "number": "100",
        "name": "TDI",
        "type": "input",
        "description": "JTAG test data input; has an internal pullup."
      },
      {
        "number": "101",
        "name": "CVDD",
        "type": "power_in",
        "description": "Dedicated 1.8-V supply for the core CPU; all CVDD pins must be connected to a common supply plane (four 0.1 µF recommended decoupling)."
      },
      {
        "number": "102",
        "name": "TMS",
        "type": "input",
        "description": "JTAG test mode select input; has an internal pullup."
      },
      {
        "number": "103",
        "name": "TRST",
        "type": "input",
        "description": "JTAG test reset input; has an internal pulldown."
      },
      {
        "number": "104",
        "name": "DR0",
        "type": "bidirectional",
        "description": "Serial port 0 data-receive input; high-impedance when SHZ or RESET is active."
      },
      {
        "number": "105",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane."
      },
      {
        "number": "106",
        "name": "FSR0",
        "type": "bidirectional",
        "description": "Serial port 0 frame-synchronization pulse for receive, which initiates the data-receive process using DR0; high-impedance when SHZ or RESET is active."
      },
      {
        "number": "107",
        "name": "CLKR0",
        "type": "bidirectional",
        "description": "Serial port 0 receive serial shift clock; high-impedance when SHZ or RESET is active."
      },
      {
        "number": "108",
        "name": "DVDD",
        "type": "power_in",
        "description": "Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling)."
      },
      {
        "number": "109",
        "name": "CLKX0",
        "type": "bidirectional",
        "description": "Serial port 0 transmit serial shift clock; high-impedance when SHZ or RESET is active."
      },
      {
        "number": "110",
        "name": "FSX0",
        "type": "bidirectional",
        "description": "Serial port 0 frame-synchronization pulse for transmit, which initiates the data-transmit process using DX0; high-impedance when SHZ or RESET is active."
      },
      {
        "number": "111",
        "name": "DX0",
        "type": "bidirectional",
        "description": "Serial port 0 data-transmit output; high-impedance when SHZ or RESET is active."
      },
      {
        "number": "112",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane."
      },
      {
        "number": "113",
        "name": "TCLK1",
        "type": "bidirectional",
        "description": "Timer 1 clock: as an input it counts external pulses, and as an output it outputs pulses generated by timer 1; high-impedance when SHZ or RESET is active."
      },
      {
        "number": "114",
        "name": "TCLK0",
        "type": "bidirectional",
        "description": "Timer 0 clock: as an input it counts external pulses, and as an output it outputs pulses generated by timer 0; high-impedance when SHZ or RESET is active."
      },
      {
        "number": "115",
        "name": "DVDD",
        "type": "power_in",
        "description": "Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling)."
      },
      {
        "number": "116",
        "name": "XF1",
        "type": "bidirectional",
        "description": "External flag 1, used as a general-purpose I/O or to support interlocked processor instructions; high-impedance when SHZ or RESET is active."
      },
      {
        "number": "117",
        "name": "XF0",
        "type": "bidirectional",
        "description": "External flag 0, used as a general-purpose I/O or to support interlocked processor instructions; high-impedance when SHZ or RESET is active."
      },
      {
        "number": "118",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane."
      },
      {
        "number": "119",
        "name": "INT3",
        "type": "input",
        "description": "External interrupt 3 input."
      },
      {
        "number": "120",
        "name": "INT2",
        "type": "input",
        "description": "External interrupt 2 input."
      },
      {
        "number": "121",
        "name": "INT1",
        "type": "input",
        "description": "External interrupt 1 input."
      },
      {
        "number": "122",
        "name": "INT0",
        "type": "input",
        "description": "External interrupt 0 input."
      },
      {
        "number": "123",
        "name": "CVDD",
        "type": "power_in",
        "description": "Dedicated 1.8-V supply for the core CPU; all CVDD pins must be connected to a common supply plane (four 0.1 µF recommended decoupling)."
      },
      {
        "number": "124",
        "name": "EDGEMODE",
        "type": "input",
        "description": "Edge-mode input that enables interrupt edge-mode detection."
      },
      {
        "number": "125",
        "name": "MCBL/MP",
        "type": "input",
        "description": "Microcomputer bootloader / microprocessor mode-select input."
      },
      {
        "number": "126",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane."
      },
      {
        "number": "127",
        "name": "RESET",
        "type": "input",
        "description": "Reset input: when low the device is held in reset, and when it returns high execution begins at the location given by the reset vector."
      },
      {
        "number": "128",
        "name": "SHZ",
        "type": "input",
        "description": "Shutdown high-impedance input that places all pins in high-impedance when active; a low on SHZ corrupts device memory and register contents, so reset with SHZ high."
      },
      {
        "number": "129",
        "name": "DVDD",
        "type": "power_in",
        "description": "Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling)."
      },
      {
        "number": "130",
        "name": "EXTCLK",
        "type": "input",
        "description": "External clock input, logic-level compatible; tie to ground if the XIN/XOUT oscillator is used."
      },
      {
        "number": "131",
        "name": "PLLVDD",
        "type": "power_in",
        "description": "Internally isolated PLL supply; connect to CVDD (1.8 V)."
      },
      {
        "number": "132",
        "name": "XOUT",
        "type": "output",
        "description": "Clock output from the internal crystal oscillator; leave unconnected if a crystal is not used."
      },
      {
        "number": "133",
        "name": "XIN",
        "type": "input",
        "description": "Clock input to the internal oscillator from a crystal; tie to ground if EXTCLK is used."
      },
      {
        "number": "134",
        "name": "PLLVSS",
        "type": "power_in",
        "description": "Internally isolated PLL ground; connect to VSS."
      },
      {
        "number": "135",
        "name": "CLKMD1",
        "type": "input",
        "description": "Clock mode select pin 1."
      },
      {
        "number": "136",
        "name": "CLKMD0",
        "type": "input",
        "description": "Clock mode select pin 0."
      },
      {
        "number": "137",
        "name": "CVDD",
        "type": "power_in",
        "description": "Dedicated 1.8-V supply for the core CPU; all CVDD pins must be connected to a common supply plane (four 0.1 µF recommended decoupling)."
      },
      {
        "number": "138",
        "name": "RSV1",
        "type": "input",
        "description": "Reserved pin; use an individual pullup to DVDD."
      },
      {
        "number": "139",
        "name": "RSV0",
        "type": "input",
        "description": "Reserved pin; use an individual pullup to DVDD."
      },
      {
        "number": "140",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane."
      },
      {
        "number": "141",
        "name": "A23",
        "type": "tri_state",
        "description": "24-bit primary-bus address output bit A23; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "142",
        "name": "A22",
        "type": "tri_state",
        "description": "24-bit primary-bus address output bit A22; high-impedance when SHZ, HOLD, or RESET is active."
      },
      {
        "number": "143",
        "name": "DVDD",
        "type": "power_in",
        "description": "Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling)."
      },
      {
        "number": "144",
        "name": "A21",
        "type": "tri_state",
        "description": "24-bit primary-bus address output bit A21; high-impedance when SHZ, HOLD, or RESET is active."
      }
    ],
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      "Package": "LQFP-144(20x20)",
      "Category": "Embedded Processors & Controllers",
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