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TMS320VC33PGE150

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Texas Instruments Digital Signal Processors (DSP/DSC), LQFP-144(20x20). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TMS320VC33PGE150

Texas Instruments · Digital Signal Processors (DSP/DSC) · LQFP-144(20x20)

TMS320VC33PGE150 from Texas Instruments, in a LQFP-144(20x20). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A20 tri_state 24-bit primary-bus address output bit A20; high-impedance when SHZ, HOLD, or RESET is active.
2 VSS power_in Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane.
3 A19 tri_state 24-bit primary-bus address output bit A19; high-impedance when SHZ, HOLD, or RESET is active.
4 A18 tri_state 24-bit primary-bus address output bit A18; high-impedance when SHZ, HOLD, or RESET is active.
5 A17 tri_state 24-bit primary-bus address output bit A17; high-impedance when SHZ, HOLD, or RESET is active.
6 DVDD power_in Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling).
7 A16 tri_state 24-bit primary-bus address output bit A16; high-impedance when SHZ, HOLD, or RESET is active.
8 A15 tri_state 24-bit primary-bus address output bit A15; high-impedance when SHZ, HOLD, or RESET is active.
9 VSS power_in Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane.
10 A14 tri_state 24-bit primary-bus address output bit A14; high-impedance when SHZ, HOLD, or RESET is active.
11 A13 tri_state 24-bit primary-bus address output bit A13; high-impedance when SHZ, HOLD, or RESET is active.
12 CVDD power_in Dedicated 1.8-V supply for the core CPU; all CVDD pins must be connected to a common supply plane (four 0.1 µF recommended decoupling).
13 A12 tri_state 24-bit primary-bus address output bit A12; high-impedance when SHZ, HOLD, or RESET is active.
14 A11 tri_state 24-bit primary-bus address output bit A11; high-impedance when SHZ, HOLD, or RESET is active.
15 DVDD power_in Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling).
16 A10 tri_state 24-bit primary-bus address output bit A10; high-impedance when SHZ, HOLD, or RESET is active.
17 A9 tri_state 24-bit primary-bus address output bit A9; high-impedance when SHZ, HOLD, or RESET is active.
18 VSS power_in Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane.
19 A8 tri_state 24-bit primary-bus address output bit A8; high-impedance when SHZ, HOLD, or RESET is active.
20 A7 tri_state 24-bit primary-bus address output bit A7; high-impedance when SHZ, HOLD, or RESET is active.
21 A6 tri_state 24-bit primary-bus address output bit A6; high-impedance when SHZ, HOLD, or RESET is active.
22 A5 tri_state 24-bit primary-bus address output bit A5; high-impedance when SHZ, HOLD, or RESET is active.
23 DVDD power_in Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling).
24 A4 tri_state 24-bit primary-bus address output bit A4; high-impedance when SHZ, HOLD, or RESET is active.
25 VSS power_in Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane.
26 A3 tri_state 24-bit primary-bus address output bit A3; high-impedance when SHZ, HOLD, or RESET is active.
27 A2 tri_state 24-bit primary-bus address output bit A2; high-impedance when SHZ, HOLD, or RESET is active.
28 CVDD power_in Dedicated 1.8-V supply for the core CPU; all CVDD pins must be connected to a common supply plane (four 0.1 µF recommended decoupling).
29 A1 tri_state 24-bit primary-bus address output bit A1; high-impedance when SHZ, HOLD, or RESET is active.
30 A0 tri_state 24-bit primary-bus address output bit A0; high-impedance when SHZ, HOLD, or RESET is active.
31 DVDD power_in Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling).
32 PAGE3 tri_state Decoded page strobe 3 for external access; high-impedance when SHZ, HOLD, or RESET is active.
33 PAGE2 tri_state Decoded page strobe 2 for external access; high-impedance when SHZ, HOLD, or RESET is active.
34 VSS power_in Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane.
35 PAGE1 tri_state Decoded page strobe 1 for external access; high-impedance when SHZ, HOLD, or RESET is active.
36 PAGE0 tri_state Decoded page strobe 0 for external access; high-impedance when SHZ, HOLD, or RESET is active.
37 DVDD power_in Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling).
38 H1 tri_state External H1 clock output; high-impedance when SHZ is active.
39 H3 tri_state External H3 clock output; high-impedance when SHZ is active.
40 VSS power_in Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane.
41 STRB tri_state Strobe output for all external accesses; high-impedance when SHZ or HOLD is active.
42 R/W tri_state Read/write output: high for a read and low for a write over the parallel interface; high-impedance when SHZ, HOLD, or RESET is active.
43 DVDD power_in Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling).
44 IACK tri_state Interrupt acknowledge output generated by the IACK instruction, which can indicate when a section of code is executing; high-impedance when SHZ is active.
45 RDY input Ready input indicating that the external device is prepared for transaction completion.
46 CVDD power_in Dedicated 1.8-V supply for the core CPU; all CVDD pins must be connected to a common supply plane (four 0.1 µF recommended decoupling).
47 HOLD input Hold input: when low, the ongoing transaction completes and the address, data, STRB and R/W outputs go high-impedance until HOLD returns high or the NOHOLD bit is set.
48 HOLDA tri_state Hold acknowledge output asserted in response to a logic-low on HOLD, indicating the primary bus is high-impedance and transactions are held; high-impedance when SHZ is active.
49 VSS power_in Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane.
50 D31 bidirectional Primary-bus 32-bit data port bit D31 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active.
51 D30 bidirectional Primary-bus 32-bit data port bit D30 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active.
52 D29 bidirectional Primary-bus 32-bit data port bit D29 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active.
53 DVDD power_in Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling).
54 D28 bidirectional Primary-bus 32-bit data port bit D28 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active.
55 D27 bidirectional Primary-bus 32-bit data port bit D27 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active.
56 VSS power_in Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane.
57 D26 bidirectional Primary-bus 32-bit data port bit D26 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active.
58 D25 bidirectional Primary-bus 32-bit data port bit D25 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active.
59 D24 bidirectional Primary-bus 32-bit data port bit D24 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active.
60 DVDD power_in Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling).
61 D23 bidirectional Primary-bus 32-bit data port bit D23 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active.
62 D22 bidirectional Primary-bus 32-bit data port bit D22 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active.
63 VSS power_in Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane.
64 D21 bidirectional Primary-bus 32-bit data port bit D21 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active.
65 D20 bidirectional Primary-bus 32-bit data port bit D20 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active.
66 CVDD power_in Dedicated 1.8-V supply for the core CPU; all CVDD pins must be connected to a common supply plane (four 0.1 µF recommended decoupling).
67 D19 bidirectional Primary-bus 32-bit data port bit D19 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active.
68 D18 bidirectional Primary-bus 32-bit data port bit D18 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active.
69 DVDD power_in Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling).
70 D17 bidirectional Primary-bus 32-bit data port bit D17 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active.
71 D16 bidirectional Primary-bus 32-bit data port bit D16 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active.
72 VSS power_in Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane.
73 D15 bidirectional Primary-bus 32-bit data port bit D15 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active.
74 D14 bidirectional Primary-bus 32-bit data port bit D14 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active.
75 D13 bidirectional Primary-bus 32-bit data port bit D13 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active.
76 D12 bidirectional Primary-bus 32-bit data port bit D12 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active.
77 DVDD power_in Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling).
78 D11 bidirectional Primary-bus 32-bit data port bit D11 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active.
79 D10 bidirectional Primary-bus 32-bit data port bit D10 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active.
80 VSS power_in Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane.
81 D9 bidirectional Primary-bus 32-bit data port bit D9 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active.
82 D8 bidirectional Primary-bus 32-bit data port bit D8 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active.
83 CVDD power_in Dedicated 1.8-V supply for the core CPU; all CVDD pins must be connected to a common supply plane (four 0.1 µF recommended decoupling).
84 D7 bidirectional Primary-bus 32-bit data port bit D7 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active.
85 D6 bidirectional Primary-bus 32-bit data port bit D6 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active.
86 DVDD power_in Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling).
87 D5 bidirectional Primary-bus 32-bit data port bit D5 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active.
88 D4 bidirectional Primary-bus 32-bit data port bit D4 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active.
89 VSS power_in Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane.
90 D3 bidirectional Primary-bus 32-bit data port bit D3 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active.
91 D2 bidirectional Primary-bus 32-bit data port bit D2 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active.
92 D1 bidirectional Primary-bus 32-bit data port bit D1 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active.
93 D0 bidirectional Primary-bus 32-bit data port bit D0 with internal bus keeper; high-impedance when SHZ, HOLD, or RESET is active.
94 DVDD power_in Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling).
95 EMU1 bidirectional JTAG emulation pin 1; use an individual pullup to DVDD.
96 EMU0 bidirectional JTAG emulation pin 0; use an individual pullup to DVDD.
97 VSS power_in Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane.
98 TCK input JTAG test clock input; has an internal pullup.
99 TDO output JTAG test data output.
100 TDI input JTAG test data input; has an internal pullup.
101 CVDD power_in Dedicated 1.8-V supply for the core CPU; all CVDD pins must be connected to a common supply plane (four 0.1 µF recommended decoupling).
102 TMS input JTAG test mode select input; has an internal pullup.
103 TRST input JTAG test reset input; has an internal pulldown.
104 DR0 bidirectional Serial port 0 data-receive input; high-impedance when SHZ or RESET is active.
105 VSS power_in Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane.
106 FSR0 bidirectional Serial port 0 frame-synchronization pulse for receive, which initiates the data-receive process using DR0; high-impedance when SHZ or RESET is active.
107 CLKR0 bidirectional Serial port 0 receive serial shift clock; high-impedance when SHZ or RESET is active.
108 DVDD power_in Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling).
109 CLKX0 bidirectional Serial port 0 transmit serial shift clock; high-impedance when SHZ or RESET is active.
110 FSX0 bidirectional Serial port 0 frame-synchronization pulse for transmit, which initiates the data-transmit process using DX0; high-impedance when SHZ or RESET is active.
111 DX0 bidirectional Serial port 0 data-transmit output; high-impedance when SHZ or RESET is active.
112 VSS power_in Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane.
113 TCLK1 bidirectional Timer 1 clock: as an input it counts external pulses, and as an output it outputs pulses generated by timer 1; high-impedance when SHZ or RESET is active.
114 TCLK0 bidirectional Timer 0 clock: as an input it counts external pulses, and as an output it outputs pulses generated by timer 0; high-impedance when SHZ or RESET is active.
115 DVDD power_in Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling).
116 XF1 bidirectional External flag 1, used as a general-purpose I/O or to support interlocked processor instructions; high-impedance when SHZ or RESET is active.
117 XF0 bidirectional External flag 0, used as a general-purpose I/O or to support interlocked processor instructions; high-impedance when SHZ or RESET is active.
118 VSS power_in Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane.
119 INT3 input External interrupt 3 input.
120 INT2 input External interrupt 2 input.
121 INT1 input External interrupt 1 input.
122 INT0 input External interrupt 0 input.
123 CVDD power_in Dedicated 1.8-V supply for the core CPU; all CVDD pins must be connected to a common supply plane (four 0.1 µF recommended decoupling).
124 EDGEMODE input Edge-mode input that enables interrupt edge-mode detection.
125 MCBL/MP input Microcomputer bootloader / microprocessor mode-select input.
126 VSS power_in Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane.
127 RESET input Reset input: when low the device is held in reset, and when it returns high execution begins at the location given by the reset vector.
128 SHZ input Shutdown high-impedance input that places all pins in high-impedance when active; a low on SHZ corrupts device memory and register contents, so reset with SHZ high.
129 DVDD power_in Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling).
130 EXTCLK input External clock input, logic-level compatible; tie to ground if the XIN/XOUT oscillator is used.
131 PLLVDD power_in Internally isolated PLL supply; connect to CVDD (1.8 V).
132 XOUT output Clock output from the internal crystal oscillator; leave unconnected if a crystal is not used.
133 XIN input Clock input to the internal oscillator from a crystal; tie to ground if EXTCLK is used.
134 PLLVSS power_in Internally isolated PLL ground; connect to VSS.
135 CLKMD1 input Clock mode select pin 1.
136 CLKMD0 input Clock mode select pin 0.
137 CVDD power_in Dedicated 1.8-V supply for the core CPU; all CVDD pins must be connected to a common supply plane (four 0.1 µF recommended decoupling).
138 RSV1 input Reserved pin; use an individual pullup to DVDD.
139 RSV0 input Reserved pin; use an individual pullup to DVDD.
140 VSS power_in Ground for both the I/O pins and the core CPU; all VSS pins must be connected to a common ground plane.
141 A23 tri_state 24-bit primary-bus address output bit A23; high-impedance when SHZ, HOLD, or RESET is active.
142 A22 tri_state 24-bit primary-bus address output bit A22; high-impedance when SHZ, HOLD, or RESET is active.
143 DVDD power_in Dedicated 3.3-V supply for the I/O pins; all DVDD pins must be connected to a common supply plane (eight 0.1 µF recommended decoupling).
144 A21 tri_state 24-bit primary-bus address output bit A21; high-impedance when SHZ, HOLD, or RESET is active.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-144(20x20)
Category Embedded Processors & Controllers
Pins 144

CAD (KiCad official)

  • Symbol: TMS320VC33PGE150
  • Footprint: Package_QFP:LQFP-144_20x20mm_P0.5mm
  • 3D model: LQFP-144(20x20) (KiCad packages3D, STEP)
  • 3D model files: tms320vc33pge150-etched.step / tms320vc33pge150-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tms320vc33pge150.step / tms320vc33pge150.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (59 pp, sha256 4e3387336ae8ae0f, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF