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TMS320LF2407APGEA

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Texas Instruments Digital Signal Processors (DSP/DSC), LQFP-144(20x20). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TMS320LF2407APGEA

Texas Instruments · Digital Signal Processors (DSP/DSC) · LQFP-144(20x20)

TMS320LF2407APGEA from Texas Instruments, in a LQFP-144(20x20). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 TRST input JTAG test reset with internal pulldown; must be driven by test system or held low during normal operation
2 TDIRB/IOPF4 output Counting direction for general-purpose timer (EVB) or GPIO; if TDIRB = 1, upward counting is selected
3 VSSO power_in I/O buffer ground; digital logic and buffer ground reference
4 VDDO power_in I/O buffer supply +3.3 V; digital logic and buffer supply voltage
5 D7 bidirectional Bit 7 of 16-bit data bus with internal pullup
6 T4PWM/T4CMP/IOPF3 output Timer 4 compare output (EVB) or GPIO with internal pullup
7 PDPINTA input Power drive protection interrupt input for EVA; falling-edge-sensitive interrupt with internal pullup
8 T3PWM/T3CMP/IOPF2 output Timer 3 compare output (EVB) or GPIO with internal pullup
9 D8 bidirectional Bit 8 of 16-bit data bus with internal pullup
10 PLLF2 passive PLL loop filter input 2; capacitor connection point for external loop filter
11 PLLF passive PLL loop filter input 1; capacitor and resistor connection point for external loop filter
12 PLLVCCA power_in PLL supply voltage 3.3 V; must be decoupled and isolated from digital supply
13 D9 bidirectional Bit 9 of 16-bit data bus with internal pullup
14 TDIRA/IOPB6 output Counting direction for general-purpose timer (EVA) or GPIO; if TDIRA = 1, upward counting is selected
15 D10 bidirectional Bit 10 of 16-bit data bus with internal pullup
16 T1PWM/T1CMP/IOPB4 output Timer 1 compare output (EVA) or GPIO with internal pullup
17 D11 bidirectional Bit 11 of 16-bit data bus with internal pullup
18 T2PWM/T2CMP/IOPB5 output Timer 2 compare output (EVA) or GPIO with internal pullup
19 W/R/IOPC0 output Write/Read qualifier signal (inverted R/W for zero-wait-state memory interface) or GPIO; normally low unless memory write operation is performed
20 D12 bidirectional Bit 12 of 16-bit data bus with internal pullup
21 XINT2/ADCSOC/IOPD0 input External user interrupt 2 and ADC start of conversion trigger or GPIO; edge-sensitive with programmable polarity and internal pullup
22 D13 bidirectional Bit 13 of 16-bit data bus with internal pullup
23 XINT1/IOPA2 input External user interrupt 1 or GPIO; edge-sensitive with programmable polarity and internal pullup
24 D14 bidirectional Bit 14 of 16-bit data bus with internal pullup
25 SCITXD/IOPA0 output SCI asynchronous serial port transmit data or GPIO with internal pullup
26 SCIRXD/IOPA1 input SCI asynchronous serial port receive data or GPIO with internal pullup
27 D15 bidirectional Bit 15 of 16-bit data bus with internal pullup
28 VSS power_in Core ground; digital logic ground reference
29 VDD power_in Core supply 3.3 V; digital logic supply voltage
30 SPISIMO/IOPC2 output SPI slave in, master out or GPIO with internal pullup
31 A15 output Bit 15 of the 16-bit address bus
32 SPISOMI/IOPC3 input SPI slave out, master in or GPIO with internal pullup
33 SPISTE/IOPC5 output SPI slave transmit enable (optional) or GPIO with internal pullup
34 A14 output Bit 14 of the 16-bit address bus
35 SPICLK/IOPC4 output SPI clock or GPIO with internal pullup
36 TMS2 input JTAG test-mode select 2 with internal pullup; used for test and emulation only; can be left unconnected in user applications
37 TCLKINA/IOPB7 input External clock input for general-purpose timer (EVA) or GPIO; timer can also use internal device clock with internal pullup
38 PWM12/IOPE6 output Compare/PWM output pin #12 (EVB) or GPIO with internal pullup
39 A13 output Bit 13 of the 16-bit address bus
40 PWM6/IOPB3 output Compare/PWM output pin #6 (EVA) or GPIO with internal pullup
41 VSSO power_in I/O buffer ground; digital logic and buffer ground reference
42 VDDO power_in I/O buffer supply +3.3 V; digital logic and buffer supply voltage
43 A12 output Bit 12 of the 16-bit address bus
44 PWM5/IOPB2 output Compare/PWM output pin #5 (EVA) or GPIO with internal pullup
45 A11 output Bit 11 of the 16-bit address bus
46 PWM11/IOPE5 output Compare/PWM output pin #11 (EVB) or GPIO with internal pullup
47 PWM4/IOPB1 output Compare/PWM output pin #4 (EVA) or GPIO with internal pullup
48 A10 output Bit 10 of the 16-bit address bus
49 VSS power_in Core ground; digital logic ground reference
50 VDD power_in Core supply 3.3 V; digital logic supply voltage
51 A9 output Bit 9 of the 16-bit address bus
52 PWM3/IOPB0 output Compare/PWM output pin #3 (EVA) or GPIO with internal pullup
53 A8 output Bit 8 of the 16-bit address bus
54 PWM2/IOPA7 output Compare/PWM output pin #2 (EVA) or GPIO with internal pullup
55 PWM10/IOPE4 output Compare/PWM output pin #10 (EVB) or GPIO with internal pullup
56 PWM1/IOPA6 output Compare/PWM output pin #1 (EVA) or GPIO with internal pullup
57 A7 output Bit 7 of the 16-bit address bus
58 VCCP (5V) power_in Flash programming voltage pin; must be connected to 5 V supply for Flash programming; can be tied to GND or 5 V during normal operation; must not be left floating
59 PWM9/IOPE3 output Compare/PWM output pin #9 (EVB) or GPIO with internal pullup
60 TP1 unconnected Test pin 1; do not connect
61 A6 output Bit 6 of the 16-bit address bus
62 PWM8/IOPE2 output Compare/PWM output pin #8 (EVB) or GPIO with internal pullup
63 TP2 unconnected Test pin 2; do not connect
64 A5 output Bit 5 of the 16-bit address bus
65 PWM7/IOPE1 output Compare/PWM output pin #7 (EVB) or GPIO with internal pullup
66 VSSO power_in I/O buffer ground; digital logic and buffer ground reference
67 VDDO power_in I/O buffer supply +3.3 V; digital logic and buffer supply voltage
68 A4 output Bit 4 of the 16-bit address bus
69 CAP6/IOPF1 input Capture input #6 (EVB) or GPIO with internal pullup
70 CANRX/IOPC7 input CAN receive data or GPIO with internal pullup; available on LF2403A
71 A3 output Bit 3 of the 16-bit address bus
72 CANTX/IOPC6 output CAN transmit data or GPIO with internal pullup; available on LF2403A
73 CLKOUT/IOPE0 output Clock output (CPU clock or watchdog clock selected by CLKSRC bit) or GPIO with internal pullup; outputs either CPU clock or watchdog clock
74 A2 output Bit 2 of the 16-bit address bus
75 CAP3/IOPA5 input Capture input #3 (EVA) or GPIO with internal pullup
76 VSSO power_in I/O buffer ground; digital logic and buffer ground reference
77 VDDO power_in I/O buffer supply +3.3 V; digital logic and buffer supply voltage
78 A1 output Bit 1 of the 16-bit address bus
79 CAP2/QEP2/IOPA4 input Capture input #2 or quadrature encoder pulse input #2 (EVA) or GPIO with internal pullup
80 A0 output Bit 0 of the 16-bit address bus
81 CAP5/QEP4/IOPF0 input Capture input #5 or quadrature encoder pulse input #4 (EVB) or GPIO with internal pullup
82 IS tri_state I/O space strobe; always high unless low-level asserted for access to relevant external I/O space; placed in high-impedance state when appropriate
83 CAP1/QEP1/IOPA3 input Capture input #1 or quadrature encoder pulse input #1 (EVA) or GPIO with internal pullup
84 PS tri_state Program space strobe; always high unless low-level asserted for access to external program memory space; placed in high-impedance state when appropriate
85 VSS power_in Core ground; digital logic ground reference
86 VDD power_in Core supply 3.3 V; digital logic supply voltage
87 DS tri_state Data space strobe; always high unless low-level asserted for access to external data memory space; placed in high-impedance state when appropriate
88 CAP4/QEP3/IOPE7 input Capture input #4 or quadrature encoder pulse input #3 (EVB) or GPIO with internal pullup
89 WE tri_state Write-enable strobe; falling edge indicates device is driving external data bus (D15-D0); active on all external program, data, and I/O writes
90 EMU0 bidirectional Emulator I/O #0 with internal pullup; used as interrupt to/from emulator system when TRST is high; defined as input/output through JTAG scan
91 EMU1/OFF output Emulator pin 1; disables all outputs when active low; when TRST is high, used as interrupt to/from emulator; when TRST is low, configured as OFF to put output drivers in high-impedance state
92 R/W tri_state Read/write qualifier signal; indicates transfer direction during communication to external device; high for read mode, low for write operation; placed in high-impedance state when appropriate
93 RD tri_state Read-enable strobe; active on all external program, data, and I/O reads; indicates active external read cycle; placed in high-impedance state when appropriate
94 VSSO power_in I/O buffer ground; digital logic and buffer ground reference
95 VDDO power_in I/O buffer supply +3.3 V; digital logic and buffer supply voltage
96 STRB tri_state External memory access strobe; always high unless asserted low to indicate external bus cycle; active for all off-chip accesses; placed in high-impedance state when appropriate
97 VIS_OE output Visibility output enable; active (low) whenever external data bus is driving as output during visibility mode for trace capabilities
98 ADCIN15 input Analog input #15 to the 10-bit ADC
99 ADCIN07 input Analog input #7 to the 10-bit ADC
100 ADCIN06 input Analog input #6 to the 10-bit ADC
101 ADCIN14 input Analog input #14 to the 10-bit ADC
102 ADCIN05 input Analog input #5 to the 10-bit ADC
103 ADCIN04 input Analog input #4 to the 10-bit ADC
104 ADCIN13 input Analog input #13 to the 10-bit ADC
105 ADCIN03 input Analog input #3 to the 10-bit ADC
106 ADCIN12 input Analog input #12 to the 10-bit ADC
107 ADCIN02 input Analog input #2 to the 10-bit ADC
108 ADCIN11 input Analog input #11 to the 10-bit ADC
109 ADCIN10 input Analog input #10 to the 10-bit ADC
110 ADCIN01 input Analog input #1 to the 10-bit ADC
111 ADCIN09 input Analog input #9 to the 10-bit ADC
112 ADCIN00 input Analog input #0 to the 10-bit ADC
113 ADCIN08 input Analog input #8 to the 10-bit ADC
114 VREFLO power_in ADC analog low-voltage reference input; must be isolated from digital ground (VSSA) to maintain ADC accuracy
115 VREFHI power_in ADC analog high-voltage reference input; must be isolated from digital supply to maintain ADC accuracy and noise immunity
116 VCCA power_in Analog supply voltage for ADC 3.3 V; should be isolated from digital supply (VDD) and VSSA from digital ground for specified accuracy
117 VSSA power_in Analog ground reference for ADC; should be isolated from digital ground (VSS) to maintain ADC accuracy and noise immunity
118 MP/MC input Microprocessor/Microcomputer mode select with internal pulldown; low at reset selects microcomputer mode (internal program memory); high selects microprocessor mode (external program memory)
119 BIO/IOPC1 input Branch control input or GPIO with internal pullup; polled by BCND pma,BIO instruction; should be pulled high if not used as branch control
120 READY input External ready signal for wait states; pulled low to add wait states for slower external devices; has internal pullup
121 BOOT_EN/XF output Boot ROM enable input or XF output; sampled during reset to update SCSR2.3 (BOOT_EN bit); driven high as XF output after reset; available only on Flash devices
122 ENA_144 input Active high to enable external interface signals with internal pulldown; if pulled low, device behaves like 2406A/2403A/2402A with no external memory
123 XTAL1/CLKIN input PLL oscillator input pin or clock source input to PLL; tied to reference crystal for crystal oscillator mode; accepts external clock signal 4-20 MHz
124 XTAL2 output Crystal output or PLL oscillator output pin; tied to reference crystal; goes into high-impedance state when EMU1/OFF is active low
125 VSSO power_in I/O buffer ground; digital logic and buffer ground reference
126 TCLKINB/IOPF5 input External clock input for general-purpose timer (EVB) or GPIO; timer can also use internal device clock with internal pullup
127 D0 bidirectional Bit 0 of 16-bit data bus with internal pullup
128 VSS power_in Core ground; digital logic ground reference
129 VDD power_in Core supply 3.3 V; digital logic supply voltage
130 D1 bidirectional Bit 1 of 16-bit data bus with internal pullup
131 IOPF6 bidirectional General-purpose I/O with internal pullup
132 D2 bidirectional Bit 2 of 16-bit data bus with internal pullup
133 RS bidirectional Device reset input and watchdog reset output; causes device to terminate execution and set PC=0; open-drain output with internal 20 µA pullup; driven low by DSP during watchdog reset
134 D3 bidirectional Bit 3 of 16-bit data bus with internal pullup
135 TCK input JTAG test clock with internal pullup; clocks TDI into selected register on rising edge
136 D4 bidirectional Bit 4 of 16-bit data bus with internal pullup
137 PDPINTB input Power drive protection interrupt input for EVB; falling-edge-sensitive interrupt; puts PWM output pins in high-impedance state for motor drive/converter abnormalities
138 D5 bidirectional Bit 5 of 16-bit data bus with internal pullup
139 TDI input JTAG test data input with internal pullup; clocked into selected register on rising edge of TCK
140 VSSO power_in I/O buffer ground; digital logic and buffer ground reference
141 VDDO power_in I/O buffer supply +3.3 V; digital logic and buffer supply voltage
142 TDO output JTAG test data output with internal pulldown; contents of selected register shifted out on falling edge of TCK
143 D6 bidirectional Bit 6 of 16-bit data bus with internal pullup
144 TMS input JTAG test-mode select with internal pullup; serial control input clocked into TAP controller on rising edge of TCK

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-144(20x20)
Category Embedded Processors & Controllers
Pins 144

CAD (KiCad official)

  • Symbol: TMS320LF2407APGEA
  • Footprint: Package_QFP:LQFP-144_20x20mm_P0.5mm
  • 3D model: LQFP-144(20x20) (KiCad packages3D, STEP)
  • 3D model files: tms320lf2407apgea-etched.step / tms320lf2407apgea-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tms320lf2407apgea.step / tms320lf2407apgea.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (141 pp, sha256 f19019cb4a75676b, retrieved 2026-10-05, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF