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TMS320LF2407APGEA
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Texas Instruments Digital Signal Processors (DSP/DSC), LQFP-144(20x20). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+180@@ -0,0 +1,180 @@+# TMS320LF2407APGEA++**Texas Instruments** · Digital Signal Processors (DSP/DSC) · LQFP-144(20x20)++TMS320LF2407APGEA from Texas Instruments, in a LQFP-144(20x20). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | TRST | input | JTAG test reset with internal pulldown; must be driven by test system or held low during normal operation |+| 2 | TDIRB/IOPF4 | output | Counting direction for general-purpose timer (EVB) or GPIO; if TDIRB = 1, upward counting is selected |+| 3 | VSSO | power_in | I/O buffer ground; digital logic and buffer ground reference |+| 4 | VDDO | power_in | I/O buffer supply +3.3 V; digital logic and buffer supply voltage |+| 5 | D7 | bidirectional | Bit 7 of 16-bit data bus with internal pullup |+| 6 | T4PWM/T4CMP/IOPF3 | output | Timer 4 compare output (EVB) or GPIO with internal pullup |+| 7 | PDPINTA | input | Power drive protection interrupt input for EVA; falling-edge-sensitive interrupt with internal pullup |+| 8 | T3PWM/T3CMP/IOPF2 | output | Timer 3 compare output (EVB) or GPIO with internal pullup |+| 9 | D8 | bidirectional | Bit 8 of 16-bit data bus with internal pullup |+| 10 | PLLF2 | passive | PLL loop filter input 2; capacitor connection point for external loop filter |+| 11 | PLLF | passive | PLL loop filter input 1; capacitor and resistor connection point for external loop filter |+| 12 | PLLVCCA | power_in | PLL supply voltage 3.3 V; must be decoupled and isolated from digital supply |+| 13 | D9 | bidirectional | Bit 9 of 16-bit data bus with internal pullup |+| 14 | TDIRA/IOPB6 | output | Counting direction for general-purpose timer (EVA) or GPIO; if TDIRA = 1, upward counting is selected |+| 15 | D10 | bidirectional | Bit 10 of 16-bit data bus with internal pullup |+| 16 | T1PWM/T1CMP/IOPB4 | output | Timer 1 compare output (EVA) or GPIO with internal pullup |+| 17 | D11 | bidirectional | Bit 11 of 16-bit data bus with internal pullup |+| 18 | T2PWM/T2CMP/IOPB5 | output | Timer 2 compare output (EVA) or GPIO with internal pullup |+| 19 | W/R/IOPC0 | output | Write/Read qualifier signal (inverted R/W for zero-wait-state memory interface) or GPIO; normally low unless memory write operation is performed |+| 20 | D12 | bidirectional | Bit 12 of 16-bit data bus with internal pullup |+| 21 | XINT2/ADCSOC/IOPD0 | input | External user interrupt 2 and ADC start of conversion trigger or GPIO; edge-sensitive with programmable polarity and internal pullup |+| 22 | D13 | bidirectional | Bit 13 of 16-bit data bus with internal pullup |+| 23 | XINT1/IOPA2 | input | External user interrupt 1 or GPIO; edge-sensitive with programmable polarity and internal pullup |+| 24 | D14 | bidirectional | Bit 14 of 16-bit data bus with internal pullup |+| 25 | SCITXD/IOPA0 | output | SCI asynchronous serial port transmit data or GPIO with internal pullup |+| 26 | SCIRXD/IOPA1 | input | SCI asynchronous serial port receive data or GPIO with internal pullup |+| 27 | D15 | bidirectional | Bit 15 of 16-bit data bus with internal pullup |+| 28 | VSS | power_in | Core ground; digital logic ground reference |+| 29 | VDD | power_in | Core supply 3.3 V; digital logic supply voltage |+| 30 | SPISIMO/IOPC2 | output | SPI slave in, master out or GPIO with internal pullup |+| 31 | A15 | output | Bit 15 of the 16-bit address bus |+| 32 | SPISOMI/IOPC3 | input | SPI slave out, master in or GPIO with internal pullup |+| 33 | SPISTE/IOPC5 | output | SPI slave transmit enable (optional) or GPIO with internal pullup |+| 34 | A14 | output | Bit 14 of the 16-bit address bus |+| 35 | SPICLK/IOPC4 | output | SPI clock or GPIO with internal pullup |+| 36 | TMS2 | input | JTAG test-mode select 2 with internal pullup; used for test and emulation only; can be left unconnected in user applications |+| 37 | TCLKINA/IOPB7 | input | External clock input for general-purpose timer (EVA) or GPIO; timer can also use internal device clock with internal pullup |+| 38 | PWM12/IOPE6 | output | Compare/PWM output pin #12 (EVB) or GPIO with internal pullup |+| 39 | A13 | output | Bit 13 of the 16-bit address bus |+| 40 | PWM6/IOPB3 | output | Compare/PWM output pin #6 (EVA) or GPIO with internal pullup |+| 41 | VSSO | power_in | I/O buffer ground; digital logic and buffer ground reference |+| 42 | VDDO | power_in | I/O buffer supply +3.3 V; digital logic and buffer supply voltage |+| 43 | A12 | output | Bit 12 of the 16-bit address bus |+| 44 | PWM5/IOPB2 | output | Compare/PWM output pin #5 (EVA) or GPIO with internal pullup |+| 45 | A11 | output | Bit 11 of the 16-bit address bus |+| 46 | PWM11/IOPE5 | output | Compare/PWM output pin #11 (EVB) or GPIO with internal pullup |+| 47 | PWM4/IOPB1 | output | Compare/PWM output pin #4 (EVA) or GPIO with internal pullup |+| 48 | A10 | output | Bit 10 of the 16-bit address bus |+| 49 | VSS | power_in | Core ground; digital logic ground reference |+| 50 | VDD | power_in | Core supply 3.3 V; digital logic supply voltage |+| 51 | A9 | output | Bit 9 of the 16-bit address bus |+| 52 | PWM3/IOPB0 | output | Compare/PWM output pin #3 (EVA) or GPIO with internal pullup |+| 53 | A8 | output | Bit 8 of the 16-bit address bus |+| 54 | PWM2/IOPA7 | output | Compare/PWM output pin #2 (EVA) or GPIO with internal pullup |+| 55 | PWM10/IOPE4 | output | Compare/PWM output pin #10 (EVB) or GPIO with internal pullup |+| 56 | PWM1/IOPA6 | output | Compare/PWM output pin #1 (EVA) or GPIO with internal pullup |+| 57 | A7 | output | Bit 7 of the 16-bit address bus |+| 58 | VCCP (5V) | power_in | Flash programming voltage pin; must be connected to 5 V supply for Flash programming; can be tied to GND or 5 V during normal operation; must not be left floating |+| 59 | PWM9/IOPE3 | output | Compare/PWM output pin #9 (EVB) or GPIO with internal pullup |+| 60 | TP1 | unconnected | Test pin 1; do not connect |+| 61 | A6 | output | Bit 6 of the 16-bit address bus |+| 62 | PWM8/IOPE2 | output | Compare/PWM output pin #8 (EVB) or GPIO with internal pullup |+| 63 | TP2 | unconnected | Test pin 2; do not connect |+| 64 | A5 | output | Bit 5 of the 16-bit address bus |+| 65 | PWM7/IOPE1 | output | Compare/PWM output pin #7 (EVB) or GPIO with internal pullup |+| 66 | VSSO | power_in | I/O buffer ground; digital logic and buffer ground reference |+| 67 | VDDO | power_in | I/O buffer supply +3.3 V; digital logic and buffer supply voltage |+| 68 | A4 | output | Bit 4 of the 16-bit address bus |+| 69 | CAP6/IOPF1 | input | Capture input #6 (EVB) or GPIO with internal pullup |+| 70 | CANRX/IOPC7 | input | CAN receive data or GPIO with internal pullup; available on LF2403A |+| 71 | A3 | output | Bit 3 of the 16-bit address bus |+| 72 | CANTX/IOPC6 | output | CAN transmit data or GPIO with internal pullup; available on LF2403A |+| 73 | CLKOUT/IOPE0 | output | Clock output (CPU clock or watchdog clock selected by CLKSRC bit) or GPIO with internal pullup; outputs either CPU clock or watchdog clock |+| 74 | A2 | output | Bit 2 of the 16-bit address bus |+| 75 | CAP3/IOPA5 | input | Capture input #3 (EVA) or GPIO with internal pullup |+| 76 | VSSO | power_in | I/O buffer ground; digital logic and buffer ground reference |+| 77 | VDDO | power_in | I/O buffer supply +3.3 V; digital logic and buffer supply voltage |+| 78 | A1 | output | Bit 1 of the 16-bit address bus |+| 79 | CAP2/QEP2/IOPA4 | input | Capture input #2 or quadrature encoder pulse input #2 (EVA) or GPIO with internal pullup |+| 80 | A0 | output | Bit 0 of the 16-bit address bus |+| 81 | CAP5/QEP4/IOPF0 | input | Capture input #5 or quadrature encoder pulse input #4 (EVB) or GPIO with internal pullup |+| 82 | IS | tri_state | I/O space strobe; always high unless low-level asserted for access to relevant external I/O space; placed in high-impedance state when appropriate |+| 83 | CAP1/QEP1/IOPA3 | input | Capture input #1 or quadrature encoder pulse input #1 (EVA) or GPIO with internal pullup |+| 84 | PS | tri_state | Program space strobe; always high unless low-level asserted for access to external program memory space; placed in high-impedance state when appropriate |+| 85 | VSS | power_in | Core ground; digital logic ground reference |+| 86 | VDD | power_in | Core supply 3.3 V; digital logic supply voltage |+| 87 | DS | tri_state | Data space strobe; always high unless low-level asserted for access to external data memory space; placed in high-impedance state when appropriate |+| 88 | CAP4/QEP3/IOPE7 | input | Capture input #4 or quadrature encoder pulse input #3 (EVB) or GPIO with internal pullup |+| 89 | WE | tri_state | Write-enable strobe; falling edge indicates device is driving external data bus (D15-D0); active on all external program, data, and I/O writes |+| 90 | EMU0 | bidirectional | Emulator I/O #0 with internal pullup; used as interrupt to/from emulator system when TRST is high; defined as input/output through JTAG scan |+| 91 | EMU1/OFF | output | Emulator pin 1; disables all outputs when active low; when TRST is high, used as interrupt to/from emulator; when TRST is low, configured as OFF to put output drivers in high-impedance state |+| 92 | R/W | tri_state | Read/write qualifier signal; indicates transfer direction during communication to external device; high for read mode, low for write operation; placed in high-impedance state when appropriate |+| 93 | RD | tri_state | Read-enable strobe; active on all external program, data, and I/O reads; indicates active external read cycle; placed in high-impedance state when appropriate |+| 94 | VSSO | power_in | I/O buffer ground; digital logic and buffer ground reference |+| 95 | VDDO | power_in | I/O buffer supply +3.3 V; digital logic and buffer supply voltage |+| 96 | STRB | tri_state | External memory access strobe; always high unless asserted low to indicate external bus cycle; active for all off-chip accesses; placed in high-impedance state when appropriate |+| 97 | VIS_OE | output | Visibility output enable; active (low) whenever external data bus is driving as output during visibility mode for trace capabilities |+| 98 | ADCIN15 | input | Analog input #15 to the 10-bit ADC |+| 99 | ADCIN07 | input | Analog input #7 to the 10-bit ADC |+| 100 | ADCIN06 | input | Analog input #6 to the 10-bit ADC |+| 101 | ADCIN14 | input | Analog input #14 to the 10-bit ADC |+| 102 | ADCIN05 | input | Analog input #5 to the 10-bit ADC |+| 103 | ADCIN04 | input | Analog input #4 to the 10-bit ADC |+| 104 | ADCIN13 | input | Analog input #13 to the 10-bit ADC |+| 105 | ADCIN03 | input | Analog input #3 to the 10-bit ADC |+| 106 | ADCIN12 | input | Analog input #12 to the 10-bit ADC |+| 107 | ADCIN02 | input | Analog input #2 to the 10-bit ADC |+| 108 | ADCIN11 | input | Analog input #11 to the 10-bit ADC |+| 109 | ADCIN10 | input | Analog input #10 to the 10-bit ADC |+| 110 | ADCIN01 | input | Analog input #1 to the 10-bit ADC |+| 111 | ADCIN09 | input | Analog input #9 to the 10-bit ADC |+| 112 | ADCIN00 | input | Analog input #0 to the 10-bit ADC |+| 113 | ADCIN08 | input | Analog input #8 to the 10-bit ADC |+| 114 | VREFLO | power_in | ADC analog low-voltage reference input; must be isolated from digital ground (VSSA) to maintain ADC accuracy |+| 115 | VREFHI | power_in | ADC analog high-voltage reference input; must be isolated from digital supply to maintain ADC accuracy and noise immunity |+| 116 | VCCA | power_in | Analog supply voltage for ADC 3.3 V; should be isolated from digital supply (VDD) and VSSA from digital ground for specified accuracy |+| 117 | VSSA | power_in | Analog ground reference for ADC; should be isolated from digital ground (VSS) to maintain ADC accuracy and noise immunity |+| 118 | MP/MC | input | Microprocessor/Microcomputer mode select with internal pulldown; low at reset selects microcomputer mode (internal program memory); high selects microprocessor mode (external program memory) |+| 119 | BIO/IOPC1 | input | Branch control input or GPIO with internal pullup; polled by BCND pma,BIO instruction; should be pulled high if not used as branch control |+| 120 | READY | input | External ready signal for wait states; pulled low to add wait states for slower external devices; has internal pullup |+| 121 | BOOT_EN/XF | output | Boot ROM enable input or XF output; sampled during reset to update SCSR2.3 (BOOT_EN bit); driven high as XF output after reset; available only on Flash devices |+| 122 | ENA_144 | input | Active high to enable external interface signals with internal pulldown; if pulled low, device behaves like 2406A/2403A/2402A with no external memory |+| 123 | XTAL1/CLKIN | input | PLL oscillator input pin or clock source input to PLL; tied to reference crystal for crystal oscillator mode; accepts external clock signal 4-20 MHz |+| 124 | XTAL2 | output | Crystal output or PLL oscillator output pin; tied to reference crystal; goes into high-impedance state when EMU1/OFF is active low |+| 125 | VSSO | power_in | I/O buffer ground; digital logic and buffer ground reference |+| 126 | TCLKINB/IOPF5 | input | External clock input for general-purpose timer (EVB) or GPIO; timer can also use internal device clock with internal pullup |+| 127 | D0 | bidirectional | Bit 0 of 16-bit data bus with internal pullup |+| 128 | VSS | power_in | Core ground; digital logic ground reference |+| 129 | VDD | power_in | Core supply 3.3 V; digital logic supply voltage |+| 130 | D1 | bidirectional | Bit 1 of 16-bit data bus with internal pullup |+| 131 | IOPF6 | bidirectional | General-purpose I/O with internal pullup |+| 132 | D2 | bidirectional | Bit 2 of 16-bit data bus with internal pullup |+| 133 | RS | bidirectional | Device reset input and watchdog reset output; causes device to terminate execution and set PC=0; open-drain output with internal 20 µA pullup; driven low by DSP during watchdog reset |+| 134 | D3 | bidirectional | Bit 3 of 16-bit data bus with internal pullup |+| 135 | TCK | input | JTAG test clock with internal pullup; clocks TDI into selected register on rising edge |+| 136 | D4 | bidirectional | Bit 4 of 16-bit data bus with internal pullup |+| 137 | PDPINTB | input | Power drive protection interrupt input for EVB; falling-edge-sensitive interrupt; puts PWM output pins in high-impedance state for motor drive/converter abnormalities |+| 138 | D5 | bidirectional | Bit 5 of 16-bit data bus with internal pullup |+| 139 | TDI | input | JTAG test data input with internal pullup; clocked into selected register on rising edge of TCK |+| 140 | VSSO | power_in | I/O buffer ground; digital logic and buffer ground reference |+| 141 | VDDO | power_in | I/O buffer supply +3.3 V; digital logic and buffer supply voltage |+| 142 | TDO | output | JTAG test data output with internal pulldown; contents of selected register shifted out on falling edge of TCK |+| 143 | D6 | bidirectional | Bit 6 of 16-bit data bus with internal pullup |+| 144 | TMS | input | JTAG test-mode select with internal pullup; serial control input clocked into TAP controller on rising edge of TCK |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | LQFP-144(20x20) |+| Category | Embedded Processors & Controllers |+| Pins | 144 |++## CAD (KiCad official)++- Symbol: `TMS320LF2407APGEA`+- Footprint: `Package_QFP:LQFP-144_20x20mm_P0.5mm`+- 3D model: LQFP-144(20x20) (KiCad packages3D, STEP)+- 3D model files: `tms320lf2407apgea-etched.step` / `tms320lf2407apgea-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tms320lf2407apgea.step` / `tms320lf2407apgea.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tms320lf2407a) (141 pp, sha256 `f19019cb4a75676b`, retrieved 2026-10-05, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tms320lf2407apgea-datasheet.pdf)
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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "embedded processors & controllers",+ "tms320lf2407apgea",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "tms320lf2407apgea.kicad_sym",+ "tms320lf2407apgea.kicad_mod",+ "tms320lf2407apgea.glb",+ "tms320lf2407apgea.step",+ "tms320lf2407apgea.lbr",+ "docs/hero.png",+ "docs/tms320lf2407apgea-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "tms320lf2407apgea-hero.glb",+ "tms320lf2407apgea-hero.overlay.json"+ ],+ "component": {+ "mpn": "TMS320LF2407APGEA",+ "manufacturer": "Texas Instruments",+ "package": "LQFP-144(20x20)",+ "pin_count": 144,+ "category": "Embedded Processors & Controllers",+ "subcategory": "Digital Signal Processors (DSP/DSC)",+ "datasheet": "https://www.ti.com/cn/lit/gpn/tms320lf2407a",+ "parts": {+ "symbol": "tms320lf2407apgea.kicad_sym",+ "footprint": "tms320lf2407apgea.kicad_mod",+ "model_3d": "tms320lf2407apgea-hero.glb",+ "model_3d_plain": "tms320lf2407apgea.glb",+ "model_3d_step": "tms320lf2407apgea-etched.step",+ "model_3d_step_plain": "tms320lf2407apgea.step",+ "lbr": "tms320lf2407apgea.lbr"+ },+ "distributor_links": {+ "lcsc": 26351,+ "digikey": "296-12548-ND",+ "mouser": "595-TMS320L2407APGEA"+ },+ "distributor_check": {+ "checked_at": "2026-10-05T20:40:09Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-12548-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "595-TMS320L2407APGEA",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "TRST",+ "type": "input",+ "description": "JTAG test reset with internal pulldown; must be driven by test system or held low during normal operation"+ },+ {+ "number": "2",+ "name": "TDIRB/IOPF4",+ "type": "output",+ "description": "Counting direction for general-purpose timer (EVB) or GPIO; if TDIRB = 1, upward counting is selected"+ },+ {+ "number": "3",+ "name": "VSSO",+ "type": "power_in",+ "description": "I/O buffer ground; digital logic and buffer ground reference"+ },+ {+ "number": "4",+ "name": "VDDO",+ "type": "power_in",+ "description": "I/O buffer supply +3.3 V; digital logic and buffer supply voltage"+ },+ {+ "number": "5",+ "name": "D7",+ "type": "bidirectional",+ "description": "Bit 7 of 16-bit data bus with internal pullup"+ },+ {+ "number": "6",+ "name": "T4PWM/T4CMP/IOPF3",+ "type": "output",+ "description": "Timer 4 compare output (EVB) or GPIO with internal pullup"+ },+ {+ "number": "7",+ "name": "PDPINTA",+ "type": "input",+ "description": "Power drive protection interrupt input for EVA; falling-edge-sensitive interrupt with internal pullup"+ },+ {+ "number": "8",+ "name": "T3PWM/T3CMP/IOPF2",+ "type": "output",+ "description": "Timer 3 compare output (EVB) or GPIO with internal pullup"+ },+ {+ "number": "9",+ "name": "D8",+ "type": "bidirectional",+ "description": "Bit 8 of 16-bit data bus with internal pullup"+ },+ {+ "number": "10",+ "name": "PLLF2",+ "type": "passive",+ "description": "PLL loop filter input 2; capacitor connection point for external loop filter"+ },+ {+ "number": "11",+ "name": "PLLF",+ "type": "passive",+ "description": "PLL loop filter input 1; capacitor and resistor connection point for external loop filter"+ },+ {+ "number": "12",+ "name": "PLLVCCA",+ "type": "power_in",+ "description": "PLL supply voltage 3.3 V; must be decoupled and isolated from digital supply"+ },+ {+ "number": "13",+ "name": "D9",+ "type": "bidirectional",+ "description": "Bit 9 of 16-bit data bus with internal pullup"+ },+ {+ "number": "14",+ "name": "TDIRA/IOPB6",+ "type": "output",+ "description": "Counting direction for general-purpose timer (EVA) or GPIO; if TDIRA = 1, upward counting is selected"+ },+ {+ "number": "15",+ "name": "D10",+ "type": "bidirectional",+ "description": "Bit 10 of 16-bit data bus with internal pullup"+ },+ {+ "number": "16",+ "name": "T1PWM/T1CMP/IOPB4",+ "type": "output",+ "description": "Timer 1 compare output (EVA) or GPIO with internal pullup"+ },+ {+ "number": "17",+ "name": "D11",+ "type": "bidirectional",+ "description": "Bit 11 of 16-bit data bus with internal pullup"+ },+ {+ "number": "18",+ "name": "T2PWM/T2CMP/IOPB5",+ "type": "output",+ "description": "Timer 2 compare output (EVA) or GPIO with internal pullup"+ },+ {+ "number": "19",+ "name": "W/R/IOPC0",+ "type": "output",+ "description": "Write/Read qualifier signal (inverted R/W for zero-wait-state memory interface) or GPIO; normally low unless memory write operation is performed"+ },+ {+ "number": "20",+ "name": "D12",+ "type": "bidirectional",+ "description": "Bit 12 of 16-bit data bus with internal pullup"+ },+ {+ "number": "21",+ "name": "XINT2/ADCSOC/IOPD0",+ "type": "input",+ "description": "External user interrupt 2 and ADC start of conversion trigger or GPIO; edge-sensitive with programmable polarity and internal pullup"+ },+ {+ "number": "22",+ "name": "D13",+ "type": "bidirectional",+ "description": "Bit 13 of 16-bit data bus with internal pullup"+ },+ {+ "number": "23",+ "name": "XINT1/IOPA2",+ "type": "input",+ "description": "External user interrupt 1 or GPIO; edge-sensitive with programmable polarity and internal pullup"+ },+ {+ "number": "24",+ "name": "D14",+ "type": "bidirectional",+ "description": "Bit 14 of 16-bit data bus with internal pullup"+ },+ {+ "number": "25",+ "name": "SCITXD/IOPA0",+ "type": "output",+ "description": "SCI asynchronous serial port transmit data or GPIO with internal pullup"+ },+ {+ "number": "26",+ "name": "SCIRXD/IOPA1",+ "type": "input",+ "description": "SCI asynchronous serial port receive data or GPIO with internal pullup"+ },+ {+ "number": "27",+ "name": "D15",+ "type": "bidirectional",+ "description": "Bit 15 of 16-bit data bus with internal pullup"+ },+ {+ "number": "28",+ "name": "VSS",+ "type": "power_in",+ "description": "Core ground; digital logic ground reference"+ },+ {+ "number": "29",+ "name": "VDD",+ "type": "power_in",+ "description": "Core supply 3.3 V; digital logic supply voltage"+ },+ {+ "number": "30",+ "name": "SPISIMO/IOPC2",+ "type": "output",+ "description": "SPI slave in, master out or GPIO with internal pullup"+ },+ {+ "number": "31",+ "name": "A15",+ "type": "output",+ "description": "Bit 15 of the 16-bit address bus"+ },+ {+ "number": "32",+ "name": "SPISOMI/IOPC3",+ "type": "input",+ "description": "SPI slave out, master in or GPIO with internal pullup"+ },+ {+ "number": "33",+ "name": "SPISTE/IOPC5",+ "type": "output",+ "description": "SPI slave transmit enable (optional) or GPIO with internal pullup"+ },+ {+ "number": "34",+ "name": "A14",+ "type": "output",+ "description": "Bit 14 of the 16-bit address bus"+ },+ {+ "number": "35",+ "name": "SPICLK/IOPC4",+ "type": "output",+ "description": "SPI clock or GPIO with internal pullup"+ },+ {+ "number": "36",+ "name": "TMS2",+ "type": "input",+ "description": "JTAG test-mode select 2 with internal pullup; used for test and emulation only; can be left unconnected in user applications"+ },+ {+ "number": "37",+ "name": "TCLKINA/IOPB7",+ "type": "input",+ "description": "External clock input for general-purpose timer (EVA) or GPIO; timer can also use internal device clock with internal pullup"+ },+ {+ "number": "38",+ "name": "PWM12/IOPE6",+ "type": "output",+ "description": "Compare/PWM output pin #12 (EVB) or GPIO with internal pullup"+ },+ {+ "number": "39",+ "name": "A13",+ "type": "output",+ "description": "Bit 13 of the 16-bit address bus"+ },+ {+ "number": "40",+ "name": "PWM6/IOPB3",+ "type": "output",+ "description": "Compare/PWM output pin #6 (EVA) or GPIO with internal pullup"+ },+ {+ "number": "41",+ "name": "VSSO",+ "type": "power_in",+ "description": "I/O buffer ground; digital logic and buffer ground reference"+ },+ {+ "number": "42",+ "name": "VDDO",+ "type": "power_in",+ "description": "I/O buffer supply +3.3 V; digital logic and buffer supply voltage"+ },+ {+ "number": "43",+ "name": "A12",+ "type": "output",+ "description": "Bit 12 of the 16-bit address bus"+ },+ {+ "number": "44",+ "name": "PWM5/IOPB2",+ "type": "output",+ "description": "Compare/PWM output pin #5 (EVA) or GPIO with internal pullup"+ },+ {+ "number": "45",+ "name": "A11",+ "type": "output",+ "description": "Bit 11 of the 16-bit address bus"+ },+ {+ "number": "46",+ "name": "PWM11/IOPE5",+ "type": "output",+ "description": "Compare/PWM output pin #11 (EVB) or GPIO with internal pullup"+ },+ {+ "number": "47",+ "name": "PWM4/IOPB1",+ "type": "output",+ "description": "Compare/PWM output pin #4 (EVA) or GPIO with internal pullup"+ },+ {+ "number": "48",+ "name": "A10",+ "type": "output",+ "description": "Bit 10 of the 16-bit address bus"+ },+ {+ "number": "49",+ "name": "VSS",+ "type": "power_in",+ "description": "Core ground; digital logic ground reference"+ },+ {+ "number": "50",+ "name": "VDD",+ "type": "power_in",+ "description": "Core supply 3.3 V; digital logic supply voltage"+ },+ {+ "number": "51",+ "name": "A9",+ "type": "output",+ "description": "Bit 9 of the 16-bit address bus"+ },+ {+ "number": "52",+ "name": "PWM3/IOPB0",+ "type": "output",+ "description": "Compare/PWM output pin #3 (EVA) or GPIO with internal pullup"+ },+ {+ "number": "53",+ "name": "A8",+ "type": "output",+ "description": "Bit 8 of the 16-bit address bus"+ },+ {+ "number": "54",+ "name": "PWM2/IOPA7",+ "type": "output",+ "description": "Compare/PWM output pin #2 (EVA) or GPIO with internal pullup"+ },+ {+ "number": "55",+ "name": "PWM10/IOPE4",+ "type": "output",+ "description": "Compare/PWM output pin #10 (EVB) or GPIO with internal pullup"+ },+ {+ "number": "56",+ "name": "PWM1/IOPA6",+ "type": "output",+ "description": "Compare/PWM output pin #1 (EVA) or GPIO with internal pullup"+ },+ {+ "number": "57",+ "name": "A7",+ "type": "output",+ "description": "Bit 7 of the 16-bit address bus"+ },+ {+ "number": "58",+ "name": "VCCP (5V)",+ "type": "power_in",+ "description": "Flash programming voltage pin; must be connected to 5 V supply for Flash programming; can be tied to GND or 5 V during normal operation; must not be left floating"+ },+ {+ "number": "59",+ "name": "PWM9/IOPE3",+ "type": "output",+ "description": "Compare/PWM output pin #9 (EVB) or GPIO with internal pullup"+ },+ {+ "number": "60",+ "name": "TP1",+ "type": "unconnected",+ "description": "Test pin 1; do not connect"+ },+ {+ "number": "61",+ "name": "A6",+ "type": "output",+ "description": "Bit 6 of the 16-bit address bus"+ },+ {+ "number": "62",+ "name": "PWM8/IOPE2",+ "type": "output",+ "description": "Compare/PWM output pin #8 (EVB) or GPIO with internal pullup"+ },+ {+ "number": "63",+ "name": "TP2",+ "type": "unconnected",+ "description": "Test pin 2; do not connect"+ },+ {+ "number": "64",+ "name": "A5",+ "type": "output",+ "description": "Bit 5 of the 16-bit address bus"+ },+ {+ "number": "65",+ "name": "PWM7/IOPE1",+ "type": "output",+ "description": "Compare/PWM output pin #7 (EVB) or GPIO with internal pullup"+ },+ {+ "number": "66",+ "name": "VSSO",+ "type": "power_in",+ "description": "I/O buffer ground; digital logic and buffer ground reference"+ },+ {+ "number": "67",+ "name": "VDDO",+ "type": "power_in",+ "description": "I/O buffer supply +3.3 V; digital logic and buffer supply voltage"+ },+ {+ "number": "68",+ "name": "A4",+ "type": "output",+ "description": "Bit 4 of the 16-bit address bus"+ },+ {+ "number": "69",+ "name": "CAP6/IOPF1",+ "type": "input",+ "description": "Capture input #6 (EVB) or GPIO with internal pullup"+ },+ {+ "number": "70",+ "name": "CANRX/IOPC7",+ "type": "input",+ "description": "CAN receive data or GPIO with internal pullup; available on LF2403A"+ },+ {+ "number": "71",+ "name": "A3",+ "type": "output",+ "description": "Bit 3 of the 16-bit address bus"+ },+ {+ "number": "72",+ "name": "CANTX/IOPC6",+ "type": "output",+ "description": "CAN transmit data or GPIO with internal pullup; available on LF2403A"+ },+ {+ "number": "73",+ "name": "CLKOUT/IOPE0",+ "type": "output",+ "description": "Clock output (CPU clock or watchdog clock selected by CLKSRC bit) or GPIO with internal pullup; outputs either CPU clock or watchdog clock"+ },+ {+ "number": "74",+ "name": "A2",+ "type": "output",+ "description": "Bit 2 of the 16-bit address bus"+ },+ {+ "number": "75",+ "name": "CAP3/IOPA5",+ "type": "input",+ "description": "Capture input #3 (EVA) or GPIO with internal pullup"+ },+ {+ "number": "76",+ "name": "VSSO",+ "type": "power_in",+ "description": "I/O buffer ground; digital logic and buffer ground reference"+ },+ {+ "number": "77",+ "name": "VDDO",+ "type": "power_in",+ "description": "I/O buffer supply +3.3 V; digital logic and buffer supply voltage"+ },+ {+ "number": "78",+ "name": "A1",+ "type": "output",+ "description": "Bit 1 of the 16-bit address bus"+ },+ {+ "number": "79",+ "name": "CAP2/QEP2/IOPA4",+ "type": "input",+ "description": "Capture input #2 or quadrature encoder pulse input #2 (EVA) or GPIO with internal pullup"+ },+ {+ "number": "80",+ "name": "A0",+ "type": "output",+ "description": "Bit 0 of the 16-bit address bus"+ },+ {+ "number": "81",+ "name": "CAP5/QEP4/IOPF0",+ "type": "input",+ "description": "Capture input #5 or quadrature encoder pulse input #4 (EVB) or GPIO with internal pullup"+ },+ {+ "number": "82",+ "name": "IS",+ "type": "tri_state",+ "description": "I/O space strobe; always high unless low-level asserted for access to relevant external I/O space; placed in high-impedance state when appropriate"+ },+ {+ "number": "83",+ "name": "CAP1/QEP1/IOPA3",+ "type": "input",+ "description": "Capture input #1 or quadrature encoder pulse input #1 (EVA) or GPIO with internal pullup"+ },+ {+ "number": "84",+ "name": "PS",+ "type": "tri_state",+ "description": "Program space strobe; always high unless low-level asserted for access to external program memory space; placed in high-impedance state when appropriate"+ },+ {+ "number": "85",+ "name": "VSS",+ "type": "power_in",+ "description": "Core ground; digital logic ground reference"+ },+ {+ "number": "86",+ "name": "VDD",+ "type": "power_in",+ "description": "Core supply 3.3 V; digital logic supply voltage"+ },+ {+ "number": "87",+ "name": "DS",+ "type": "tri_state",+ "description": "Data space strobe; always high unless low-level asserted for access to external data memory space; placed in high-impedance state when appropriate"+ },+ {+ "number": "88",+ "name": "CAP4/QEP3/IOPE7",+ "type": "input",+ "description": "Capture input #4 or quadrature encoder pulse input #3 (EVB) or GPIO with internal pullup"+ },+ {+ "number": "89",+ "name": "WE",+ "type": "tri_state",+ "description": "Write-enable strobe; falling edge indicates device is driving external data bus (D15-D0); active on all external program, data, and I/O writes"+ },+ {+ "number": "90",+ "name": "EMU0",+ "type": "bidirectional",+ "description": "Emulator I/O #0 with internal pullup; used as interrupt to/from emulator system when TRST is high; defined as input/output through JTAG scan"+ },+ {+ "number": "91",+ "name": "EMU1/OFF",+ "type": "output",+ "description": "Emulator pin 1; disables all outputs when active low; when TRST is high, used as interrupt to/from emulator; when TRST is low, configured as OFF to put output drivers in high-impedance state"+ },+ {+ "number": "92",+ "name": "R/W",+ "type": "tri_state",+ "description": "Read/write qualifier signal; indicates transfer direction during communication to external device; high for read mode, low for write operation; placed in high-impedance state when appropriate"+ },+ {+ "number": "93",+ "name": "RD",+ "type": "tri_state",+ "description": "Read-enable strobe; active on all external program, data, and I/O reads; indicates active external read cycle; placed in high-impedance state when appropriate"+ },+ {+ "number": "94",+ "name": "VSSO",+ "type": "power_in",+ "description": "I/O buffer ground; digital logic and buffer ground reference"+ },+ {+ "number": "95",+ "name": "VDDO",+ "type": "power_in",+ "description": "I/O buffer supply +3.3 V; digital logic and buffer supply voltage"+ },+ {+ "number": "96",+ "name": "STRB",+ "type": "tri_state",+ "description": "External memory access strobe; always high unless asserted low to indicate external bus cycle; active for all off-chip accesses; placed in high-impedance state when appropriate"+ },+ {+ "number": "97",+ "name": "VIS_OE",+ "type": "output",+ "description": "Visibility output enable; active (low) whenever external data bus is driving as output during visibility mode for trace capabilities"+ },+ {+ "number": "98",+ "name": "ADCIN15",+ "type": "input",+ "description": "Analog input #15 to the 10-bit ADC"+ },+ {+ "number": "99",+ "name": "ADCIN07",+ "type": "input",+ "description": "Analog input #7 to the 10-bit ADC"+ },+ {+ "number": "100",+ "name": "ADCIN06",+ "type": "input",+ "description": "Analog input #6 to the 10-bit ADC"+ },+ {+ "number": "101",+ "name": "ADCIN14",+ "type": "input",+ "description": "Analog input #14 to the 10-bit ADC"+ },+ {+ "number": "102",+ "name": "ADCIN05",+ "type": "input",+ "description": "Analog input #5 to the 10-bit ADC"+ },+ {+ "number": "103",+ "name": "ADCIN04",+ "type": "input",+ "description": "Analog input #4 to the 10-bit ADC"+ },+ {+ "number": "104",+ "name": "ADCIN13",+ "type": "input",+ "description": "Analog input #13 to the 10-bit ADC"+ },+ {+ "number": "105",+ "name": "ADCIN03",+ "type": "input",+ "description": "Analog input #3 to the 10-bit ADC"+ },+ {+ "number": "106",+ "name": "ADCIN12",+ "type": "input",+ "description": "Analog input #12 to the 10-bit ADC"+ },+ {+ "number": "107",+ "name": "ADCIN02",+ "type": "input",+ "description": "Analog input #2 to the 10-bit ADC"+ },+ {+ "number": "108",+ "name": "ADCIN11",+ "type": "input",+ "description": "Analog input #11 to the 10-bit ADC"+ },+ {+ "number": "109",+ "name": "ADCIN10",+ "type": "input",+ "description": "Analog input #10 to the 10-bit ADC"+ },+ {+ "number": "110",+ "name": "ADCIN01",+ "type": "input",+ "description": "Analog input #1 to the 10-bit ADC"+ },+ {+ "number": "111",+ "name": "ADCIN09",+ "type": "input",+ "description": "Analog input #9 to the 10-bit ADC"+ },+ {+ "number": "112",+ "name": "ADCIN00",+ "type": "input",+ "description": "Analog input #0 to the 10-bit ADC"+ },+ {+ "number": "113",+ "name": "ADCIN08",+ "type": "input",+ "description": "Analog input #8 to the 10-bit ADC"+ },+ {+ "number": "114",+ "name": "VREFLO",+ "type": "power_in",+ "description": "ADC analog low-voltage reference input; must be isolated from digital ground (VSSA) to maintain ADC accuracy"+ },+ {+ "number": "115",+ "name": "VREFHI",+ "type": "power_in",+ "description": "ADC analog high-voltage reference input; must be isolated from digital supply to maintain ADC accuracy and noise immunity"+ },+ {+ "number": "116",+ "name": "VCCA",+ "type": "power_in",+ "description": "Analog supply voltage for ADC 3.3 V; should be isolated from digital supply (VDD) and VSSA from digital ground for specified accuracy"+ },+ {+ "number": "117",+ "name": "VSSA",+ "type": "power_in",+ "description": "Analog ground reference for ADC; should be isolated from digital ground (VSS) to maintain ADC accuracy and noise immunity"+ },+ {+ "number": "118",+ "name": "MP/MC",+ "type": "input",+ "description": "Microprocessor/Microcomputer mode select with internal pulldown; low at reset selects microcomputer mode (internal program memory); high selects microprocessor mode (external program memory)"+ },+ {+ "number": "119",+ "name": "BIO/IOPC1",+ "type": "input",+ "description": "Branch control input or GPIO with internal pullup; polled by BCND pma,BIO instruction; should be pulled high if not used as branch control"+ },+ {+ "number": "120",+ "name": "READY",+ "type": "input",+ "description": "External ready signal for wait states; pulled low to add wait states for slower external devices; has internal pullup"+ },+ {+ "number": "121",+ "name": "BOOT_EN/XF",+ "type": "output",+ "description": "Boot ROM enable input or XF output; sampled during reset to update SCSR2.3 (BOOT_EN bit); driven high as XF output after reset; available only on Flash devices"+ },+ {+ "number": "122",+ "name": "ENA_144",+ "type": "input",+ "description": "Active high to enable external interface signals with internal pulldown; if pulled low, device behaves like 2406A/2403A/2402A with no external memory"+ },+ {+ "number": "123",+ "name": "XTAL1/CLKIN",+ "type": "input",+ "description": "PLL oscillator input pin or clock source input to PLL; tied to reference crystal for crystal oscillator mode; accepts external clock signal 4-20 MHz"+ },+ {+ "number": "124",+ "name": "XTAL2",+ "type": "output",+ "description": "Crystal output or PLL oscillator output pin; tied to reference crystal; goes into high-impedance state when EMU1/OFF is active low"+ },+ {+ "number": "125",+ "name": "VSSO",+ "type": "power_in",+ "description": "I/O buffer ground; digital logic and buffer ground reference"+ },+ {+ "number": "126",+ "name": "TCLKINB/IOPF5",+ "type": "input",+ "description": "External clock input for general-purpose timer (EVB) or GPIO; timer can also use internal device clock with internal pullup"+ },+ {+ "number": "127",+ "name": "D0",+ "type": "bidirectional",+ "description": "Bit 0 of 16-bit data bus with internal pullup"+ },+ {+ "number": "128",+ "name": "VSS",+ "type": "power_in",+ "description": "Core ground; digital logic ground reference"+ },+ {+ "number": "129",+ "name": "VDD",+ "type": "power_in",+ "description": "Core supply 3.3 V; digital logic supply voltage"+ },+ {+ "number": "130",+ "name": "D1",+ "type": "bidirectional",+ "description": "Bit 1 of 16-bit data bus with internal pullup"+ },+ {+ "number": "131",+ "name": "IOPF6",+ "type": "bidirectional",+ "description": "General-purpose I/O with internal pullup"+ },+ {+ "number": "132",+ "name": "D2",+ "type": "bidirectional",+ "description": "Bit 2 of 16-bit data bus with internal pullup"+ },+ {+ "number": "133",+ "name": "RS",+ "type": "bidirectional",+ "description": "Device reset input and watchdog reset output; causes device to terminate execution and set PC=0; open-drain output with internal 20 µA pullup; driven low by DSP during watchdog reset"+ },+ {+ "number": "134",+ "name": "D3",+ "type": "bidirectional",+ "description": "Bit 3 of 16-bit data bus with internal pullup"+ },+ {+ "number": "135",+ "name": "TCK",+ "type": "input",+ "description": "JTAG test clock with internal pullup; clocks TDI into selected register on rising edge"+ },+ {+ "number": "136",+ "name": "D4",+ "type": "bidirectional",+ "description": "Bit 4 of 16-bit data bus with internal pullup"+ },+ {+ "number": "137",+ "name": "PDPINTB",+ "type": "input",+ "description": "Power drive protection interrupt input for EVB; falling-edge-sensitive interrupt; puts PWM output pins in high-impedance state for motor drive/converter abnormalities"+ },+ {+ "number": "138",+ "name": "D5",+ "type": "bidirectional",+ "description": "Bit 5 of 16-bit data bus with internal pullup"+ },+ {+ "number": "139",+ "name": "TDI",+ "type": "input",+ "description": "JTAG test data input with internal pullup; clocked into selected register on rising edge of TCK"+ },+ {+ "number": "140",+ "name": "VSSO",+ "type": "power_in",+ "description": "I/O buffer ground; digital logic and buffer ground reference"+ },+ {+ "number": "141",+ "name": "VDDO",+ "type": "power_in",+ "description": "I/O buffer supply +3.3 V; digital logic and buffer supply voltage"+ },+ {+ "number": "142",+ "name": "TDO",+ "type": "output",+ "description": "JTAG test data output with internal pulldown; contents of selected register shifted out on falling edge of TCK"+ },+ {+ "number": "143",+ "name": "D6",+ "type": "bidirectional",+ "description": "Bit 6 of 16-bit data bus with internal pullup"+ },+ {+ "number": "144",+ "name": "TMS",+ "type": "input",+ "description": "JTAG test-mode select with internal pullup; serial control input clocked into TAP controller on rising edge of TCK"+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Pins with dual function (e.g., PWM/GPIO, ADC input/GPIO, etc.) are listed with primary datasheet fun; Data bus (D0-D15) and address bus (A0-A15) pins are bidirectional or tri-state outputs; these pins g; Memory control strobes (DS, IS, PS, RD, WE, STRB, R/W) are tri-state outputs; placement in high-impe"+ ],+ "pages_sent": 48,+ "cost_usd": 0.5609,+ "at": "2026-10-05T20:39:29"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tms320lf2407a",+ "pages": 141,+ "sha256": "f19019cb4a75676b",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 144,+ "described": 144,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}