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TMS320F28062FPZT

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Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TMS320F28062FPZT

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

TMS320F28062FPZT from Texas Instruments, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GPIO42 bidirectional General-purpose I/O 42 (I/O/Z, internal pullup, PWM pin pullups not enabled at reset); alternates are EPWM8A output with HRPWM, TZ1 trip-zone input and COMP1OUT comparator 1 direct output.
2 GPIO23/EQEP1I/MFSXA/SCIRXDB bidirectional General-purpose I/O 23 (I/O/Z, internal pullup); alternates are eQEP1 index, McBSP-A transmit frame sync and SCI-B receive data.
3 VDD power_in CPU and logic digital power pin; when using the internal VREG, place one 1.2-µF capacitor between each VDD pin and ground.
4 VSS power_in Digital ground pin.
5 VDDIO power_in Digital I/O buffer power pin; single supply source when VREG is enabled, with a decoupling capacitor on each pin.
6 GPIO20/EQEP1A/MDXA/COMP1OUT bidirectional General-purpose I/O 20 (I/O/Z, internal pullup); alternates are eQEP1 input A, McBSP transmit serial data and COMP1OUT comparator 1 direct output.
7 GPIO21/EQEP1B/MDRA/COMP2OUT bidirectional General-purpose I/O 21 (I/O/Z, internal pullup); alternates are eQEP1 input B, McBSP receive serial data and COMP2OUT comparator 2 direct output.
8 GPIO43 bidirectional General-purpose I/O 43 (I/O/Z, internal pullup); alternates are EPWM8B output, TZ2 trip-zone input and COMP2OUT comparator 2 direct output.
9 GPIO4/EPWM3A bidirectional General-purpose I/O 4 (I/O/Z, internal pullup, PWM pin pullups not enabled at reset); alternate is EPWM3A output with HRPWM channel.
10 GPIO5/EPWM3B/SPISIMOA/ECAP1 bidirectional General-purpose I/O 5 (I/O/Z, internal pullup); alternates are EPWM3B output, SPI-A slave-in/master-out and eCAP1 input/output.
11 XRS bidirectional Device reset input and watchdog reset output (open-drain with internal pullup); a 2.2 kΩ to 10 kΩ resistor to VDDIO is recommended and any capacitor to VSS should be 100 nF or smaller.
12 TRST input JTAG test reset with internal pulldown; must be maintained low during normal device operation and an external pulldown (2.2 kΩ generally adequate) is required.
13 VDDIO power_in Digital I/O buffer power pin; single supply source when VREG is enabled, with a decoupling capacitor on each pin.
14 VDD power_in CPU and logic digital power pin; when using the internal VREG, place one 1.2-µF capacitor between each VDD pin and ground.
15 VSS power_in Digital ground pin.
16 ADCINA7 input ADC Group A, channel 7 analog input.
17 ADCINA6/COMP3A/AIO6 input ADC Group A, channel 6 analog input; also comparator 3A input and digital AIO6 (AIO pins have no internal pullup).
18 ADCINA5 input ADC Group A, channel 5 analog input.
19 ADCINA4/COMP2A/AIO4 input ADC Group A, channel 4 analog input; also comparator 2A input and digital AIO4 (AIO pins have no internal pullup).
20 ADCINA3 input ADC Group A, channel 3 analog input.
21 ADCINA2/COMP1A/AIO2 input ADC Group A, channel 2 analog input; also comparator 1A input and digital AIO2 (AIO pins have no internal pullup).
22 ADCINA1 input ADC Group A, channel 1 analog input.
23 ADCINA0 input ADC Group A, channel 0 analog input; on the 100-pin package this is a separate pin from VREFHI (pin 24).
24 VREFHI input ADC external reference high, used only in ADC external reference mode; VREFHI must not exceed VDDA.
25 VDDA power_in Analog power pin; tie with a 2.2-µF capacitor (typical) close to the pin.
26 VSSA power_in Analog ground pin.
27 VREFLO input ADC external reference low; equals VSSA in the internal reference mode.
28 ADCINB0 input ADC Group B, channel 0 analog input.
29 ADCINB1 input ADC Group B, channel 1 analog input.
30 ADCINB2/COMP1B/AIO10 input ADC Group B, channel 2 analog input; also comparator 1B input and digital AIO10 (AIO pins have no internal pullup).
31 ADCINB3 input ADC Group B, channel 3 analog input.
32 ADCINB4/COMP2B/AIO12 input ADC Group B, channel 4 analog input; also comparator 2B input and digital AIO12 (AIO pins have no internal pullup).
33 ADCINB5 input ADC Group B, channel 5 analog input.
34 ADCINB6/COMP3B/AIO14 input ADC Group B, channel 6 analog input; also comparator 3B input and digital AIO14 (AIO pins have no internal pullup).
35 ADCINB7 input ADC Group B, channel 7 analog input.
36 VSS power_in Digital ground pin.
37 VDD power_in CPU and logic digital power pin; when using the internal VREG, place one 1.2-µF capacitor between each VDD pin and ground.
38 VDDIO power_in Digital I/O buffer power pin; single supply source when VREG is enabled, with a decoupling capacitor on each pin.
39 GPIO25/ECAP2/EQEP2B/SPISOMIB bidirectional General-purpose I/O 25 (I/O/Z, internal pullup); alternates are eCAP2 input/output, eQEP2 input B (PZ/PZP only) and SPI-B slave-out/master-in.
40 GPIO31/CANTXA/EQEP2S/EPWM8A bidirectional General-purpose I/O 31 (I/O/Z, internal pullup); alternates are CAN transmit, eQEP2 strobe (PZ/PZP only) and EPWM8A output.
41 GPIO30/CANRXA/EQEP2I/EPWM7A bidirectional General-purpose I/O 30 (I/O/Z, internal pullup); alternates are CAN receive, eQEP2 index (PZ/PZP only) and EPWM7A output.
42 GPIO50/EQEP1A/MDXA/TZ1 bidirectional General-purpose I/O 50 (I/O/Z, internal pullup); alternates are eQEP1 input A, McBSP transmit serial data and TZ1 trip-zone input.
43 GPIO29/SCITXDA/SCLA/TZ3 bidirectional General-purpose I/O 29 (I/O/Z, internal pullup); alternates are SCI-A transmit data, I2C clock (open-drain) and TZ3 trip-zone input.
44 GPIO12 bidirectional General-purpose I/O 12 (I/O/Z, internal pullup); alternates are TZ1 trip-zone input, SCI-A transmit data and SPI-B slave-in/master-out.
45 TEST2 bidirectional Test pin reserved for TI; must be left unconnected.
46 VDD3VFL power_in 3.3-V flash core power pin; this pin should be connected to 3.3 V at all times.
47 VSS power_in Digital ground pin.
48 GPIO51/EQEP1B/MDRA/TZ2 bidirectional General-purpose I/O 51 (I/O/Z, internal pullup); alternates are eQEP1 input B, McBSP receive serial data and TZ2 trip-zone input.
49 GPIO9/EPWM5B/SCITXDB/ECAP3 bidirectional General-purpose I/O 9 (I/O/Z, internal pullup, PWM pin pullups not enabled at reset); alternates are EPWM5B output, SCI-B transmit data and eCAP3 input/output.
50 GPIO28/SCIRXDA/SDAA/TZ2 bidirectional General-purpose I/O 28 (I/O/Z, internal pullup); alternates are SCI-A receive data, I2C data (open-drain) and TZ2 trip-zone input.
51 GPIO18/SPICLKA/SCITXDB/XCLKOUT bidirectional General-purpose I/O 18 (I/O/Z, internal pullup); alternates are SPI-A clock, SCI-B transmit data and XCLKOUT (SYSCLKOUT-derived clock, reset value SYSCLKOUT/4).
52 GPIO17/SPISOMIA/TZ3 bidirectional General-purpose I/O 17 (I/O/Z, internal pullup); alternates are SPI-A slave-out/master-in and TZ3 trip-zone input.
53 GPIO52/EQEP1S/MCLKXA/TZ3 bidirectional General-purpose I/O 52 (I/O/Z, internal pullup); alternates are eQEP1 strobe, McBSP transmit clock and TZ3 trip-zone input.
54 GPIO8/EPWM5A/ADCSOCAO bidirectional General-purpose I/O 8 (I/O/Z, internal pullup, PWM pin pullups not enabled at reset); alternates are EPWM5A output with HRPWM channel and ADC start-of-conversion A output.
55 GPIO16/SPISIMOA/TZ2 bidirectional General-purpose I/O 16 (I/O/Z, internal pullup); alternates are SPI-A slave-in/master-out and TZ2 trip-zone input.
56 GPIO44/MFSRA/SCIRXDB/EPWM7B bidirectional General-purpose I/O 44 (I/O/Z, internal pullup); alternates are McBSP receive frame sync, SCI-B receive data and EPWM7B output.
57 GPIO7/EPWM4B/SCIRXDA/ECAP2 bidirectional General-purpose I/O 7 (I/O/Z, internal pullup, PWM pin pullups not enabled at reset); alternates are EPWM4B output, SCI-A receive data and eCAP2 input/output.
58 GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO bidirectional General-purpose I/O 6 (I/O/Z, internal pullup, PWM pin pullups not enabled at reset); alternates are EPWM4A output with HRPWM channel, external ePWM sync input and sync output.
59 X2 output On-chip crystal oscillator output; a quartz crystal or ceramic resonator is connected across X1 and X2, and X2 must be left unconnected if not used.
60 X1 input On-chip 1.8-V crystal oscillator input; a crystal or resonator connects across X1 and X2, and the pin must be tied to GND if not used.
61 VDDIO power_in Digital I/O buffer power pin; single supply source when VREG is enabled, with a decoupling capacitor on each pin.
62 VSS power_in Digital ground pin.
63 VDD power_in CPU and logic digital power pin; when using the internal VREG, place one 1.2-µF capacitor between each VDD pin and ground.
64 GPIO19 bidirectional General-purpose I/O 19 (I/O/Z, internal pullup); XCLKIN external oscillator input path is not gated by the mux, so it must not be enabled for clocking when used as another peripheral; may glitch at power-up when VREG is used.
65 GPIO53/EQEP1I/MFSXA bidirectional General-purpose I/O 53 (I/O/Z, internal pullup); alternates are eQEP1 index and McBSP transmit frame sync.
66 GPIO39 bidirectional General-purpose I/O 39 (I/O/Z, internal pullup); no peripheral alternate functions are listed for this pin.
67 GPIO38/XCLKIN/TCK bidirectional General-purpose I/O 38 (I/O/Z, default at reset is GPIO38 selection for XCLKIN); TCK is the JTAG test clock with internal pullup and this pin may glitch at power-up when VREG is used.
68 GPIO34/COMP2OUT/COMP3OUT bidirectional General-purpose I/O 34 (I/O/Z, internal pullup); alternates are COMP2OUT and COMP3OUT comparator direct outputs; this pin may glitch at power-up when VREG is used.
69 GPIO54/SPISIMOA/EQEP2A/HRCAP1 bidirectional General-purpose I/O 54 (I/O/Z, internal pullup); alternates are SPI-A slave-in/master-out, eQEP2 input A and HRCAP1 high-resolution capture input.
70 GPIO37/TDO tri_state General-purpose I/O 37 (I/O/Z); JTAG scan data output TDO with 8-mA drive, shifted out on the falling edge of TCK, and may glitch at power-up when VREG is used.
71 GPIO35/TDI bidirectional General-purpose I/O 35 (I/O/Z); JTAG test data input TDI with internal pullup, clocked into the selected register on the rising edge of TCK, and may glitch at power-up when VREG is used.
72 GPIO36/TMS bidirectional General-purpose I/O 36 (I/O/Z); JTAG test-mode select TMS with internal pullup, clocked into the TAP controller on the rising edge of TCK, and may glitch at power-up when VREG is used.
73 GPIO11/EPWM6B/SCIRXDB/ECAP1 bidirectional General-purpose I/O 11 (I/O/Z, internal pullup, PWM pin pullups not enabled at reset); alternates are EPWM6B output, SCI-B receive data and eCAP1 input/output.
74 GPIO10/EPWM6A/ADCSOCBO bidirectional General-purpose I/O 10 (I/O/Z, internal pullup, PWM pin pullups not enabled at reset); alternates are EPWM6A output with HRPWM channel and ADC start-of-conversion B output.
75 GPIO55/SPISOMIA/EQEP2B/HRCAP2 bidirectional General-purpose I/O 55 (I/O/Z, internal pullup); alternates are SPI-A slave-out/master-in, eQEP2 input B and HRCAP2 high-resolution capture input.
76 GPIO41/EPWM7B/SCIRXDB bidirectional General-purpose I/O 41 (I/O/Z, internal pullup); alternates are EPWM7B output and SCI-B receive data.
77 GPIO27/HRCAP2/EQEP2S/SPISTEB/USB0DM bidirectional General-purpose I/O 27 (I/O/Z, internal pullup); alternates are HRCAP2 input, eQEP2 strobe, SPI-B slave transmit enable and USB0DM negative differential signal (enabled via USBIOEN in GPACTRL2); may glitch at power-up when VREG is used.
78 GPIO26/ECAP3/EQEP2I/SPICLKB/USB0DP bidirectional General-purpose I/O 26 (I/O/Z, internal pullup); alternates are eCAP3 input/output, eQEP2 index, SPI-B clock and USB0DP positive differential signal (enabled via USBIOEN in GPACTRL2); may glitch at power-up when VREG is used.
79 VDDIO power_in Digital I/O buffer power pin; single supply source when VREG is enabled, with a decoupling capacitor on each pin.
80 VSS power_in Digital ground pin.
81 VDD power_in CPU and logic digital power pin; when using the internal VREG, place one 1.2-µF capacitor between each VDD pin and ground.
82 GPIO40/EPWM7A/SCITXDB bidirectional General-purpose I/O 40 (I/O/Z, internal pullup, PWM pin pullups not enabled at reset); alternates are EPWM7A output with HRPWM channel and SCI-B transmit data.
83 GPIO3/EPWM2B/SPISOMIA/COMP2OUT bidirectional General-purpose I/O 3 (I/O/Z, internal pullup); alternates are EPWM2B output, SPI-A slave-out/master-in and COMP2OUT comparator 2 direct output.
84 GPIO2/EPWM2A bidirectional General-purpose I/O 2 (I/O/Z, internal pullup, PWM pin pullups not enabled at reset); alternate is EPWM2A output with HRPWM channel.
85 GPIO56/SPICLKA/EQEP2I/HRCAP3 bidirectional General-purpose I/O 56 (I/O/Z, internal pullup); alternates are SPI-A clock, eQEP2 index and HRCAP3 high-resolution capture input.
86 GPIO1/EPWM1B/COMP1OUT bidirectional General-purpose I/O 1 (I/O/Z, internal pullup, PWM pin pullups not enabled at reset); alternates are EPWM1B output and COMP1OUT comparator 1 direct output.
87 GPIO0/EPWM1A bidirectional General-purpose I/O 0 (I/O/Z, internal pullup, PWM pin pullups not enabled at reset); alternate is EPWM1A output with HRPWM channel.
88 GPIO15/ECAP2/SCIRXDB/SPISTEB bidirectional General-purpose I/O 15 (I/O/Z, internal pullup); alternates are eCAP2 input/output, SCI-B receive data and SPI-B slave transmit enable.
89 GPIO57 bidirectional General-purpose I/O 57 (I/O/Z, internal pullup); alternates are SPI-A slave transmit enable, eQEP2 strobe and HRCAP4 high-resolution capture input.
90 VREGENZ input Internal voltage regulator enable with internal pulldown; tie to VSS to enable the internal 1.8-V VREG, or to VDDIO to disable it and use an external 1.8-V supply.
91 VDD power_in CPU and logic digital power pin; when using the internal VREG, place one 1.2-µF capacitor between each VDD pin and ground.
92 VSS power_in Digital ground pin.
93 VDDIO power_in Digital I/O buffer power pin; single supply source when VREG is enabled, with a decoupling capacitor on each pin.
94 GPIO58/MCLKRA/SCITXDB/EPWM7A bidirectional General-purpose I/O 58 (I/O/Z, internal pullup); alternates are McBSP receive clock, SCI-B transmit data and EPWM7A output.
95 GPIO13 bidirectional General-purpose I/O 13 (I/O/Z, internal pullup); alternates are TZ2 trip-zone input and SPI-B slave-out/master-in.
96 GPIO14 bidirectional General-purpose I/O 14 (I/O/Z, internal pullup); alternates are TZ3 trip-zone input, SCI-B transmit data and SPI-B clock.
97 GPIO24/ECAP1/EQEP2A/SPISIMOB bidirectional General-purpose I/O 24 (I/O/Z, internal pullup); alternates are eCAP1 input/output, eQEP2 input A (PZ/PZP only) and SPI-B slave-in/master-out.
98 GPIO22/EQEP1S/MCLKXA/SCITXDB bidirectional General-purpose I/O 22 (I/O/Z, internal pullup); alternates are eQEP1 strobe, McBSP transmit clock and SCI-B transmit data.
99 GPIO32/SDAA/EPWMSYNCI/ADCSOCAO bidirectional General-purpose I/O 32 (I/O/Z, internal pullup); alternates are I2C data (open-drain), external ePWM sync input and ADC start-of-conversion A output.
100 GPIO33/SCLA/EPWMSYNCO/ADCSOCBO bidirectional General-purpose I/O 33 (I/O/Z, internal pullup); alternates are I2C clock (open-drain), external ePWM sync output and ADC start-of-conversion B output; may glitch at power-up when VREG is used.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

CAD (KiCad official)

  • Symbol: TMS320F28062FPZT
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: tms320f28062fpzt-etched.step / tms320f28062fpzt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tms320f28062fpzt.step / tms320f28062fpzt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (206 pp, sha256 3033efed856fc72a, retrieved 2026-10-07, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF