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TMS320F28034PAGS

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Texas Instruments Microcontrollers (MCU/MPU/SOC), TQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TMS320F28034PAGS

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · TQFP-64(10x10)

TMS320F28034PAGS from Texas Instruments, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GPIO22/EQEP1S/LINTXA bidirectional General-purpose I/O GPIO22 with internal pull-up selectable per pin; alternate functions are EQEP1S strobe I/O and LINTXA LIN transmit output.
2 GPIO32/SDAA/EPWMSYNCI/ADCSOCAO bidirectional General-purpose I/O GPIO32 whose alternate I2C data SDAA is an open-drain I/O, with EPWMSYNCI input and ADCSOCAO output as other alternate functions.
3 GPIO33/SCLA/EPWMSYNCO/ADCSOCBO bidirectional General-purpose I/O GPIO33 whose alternate I2C clock SCLA is an open-drain I/O, with EPWMSYNCO and ADCSOCBO outputs as other alternate functions.
4 GPIO23/EQEP1I/LINRXA bidirectional General-purpose I/O GPIO23 with alternate functions EQEP1I index I/O and LINRXA LIN receive input.
5 VDD power_in CPU and logic digital supply; when the internal VREG is used, a 1.2 µF (minimum) capacitor must be placed between each VDD pin and ground.
6 VSS power_in Digital ground pin.
7 XRS bidirectional Device reset input and watchdog reset output; open-drain with internal pull-up, driven low on power-on/brown-out, with a 2.2 kΩ to 10 kΩ resistor to VDDIO recommended.
8 TRST input JTAG test reset with internal pull-down that must be held low during normal device operation and requires an external pull-up (2.2 kΩ typical, board-dependent).
9 ADCINA7 input ADC group A channel 7 analog input.
10 ADCINA6/COMP3A/AIO6 input ADC group A channel 6 analog input, multiplexed with comparator 3A input and digital AIO6.
11 ADCINA4/COMP2A/AIO4 input ADC group A channel 4 analog input, multiplexed with comparator 2A input and digital AIO4.
12 ADCINA3 input ADC group A channel 3 analog input.
13 ADCINA2/COMP1A/AIO2 input ADC group A channel 2 analog input, multiplexed with comparator 1A input and digital AIO2.
14 ADCINA1 input ADC group A channel 1 analog input.
15 ADCINA0/VREFHI input ADC group A channel 0 input that shares the pin with VREFHI (external ADC reference high, used only in external reference mode); the two functions cannot be used at the same time.
16 VDDA power_in Analog power pin; a 2.2 µF capacitor (typical) should be connected near this pin.
17 VSSA/VREFLO power_in Analog ground pin; VREFLO is always connected to VSSA on the 64-pin PAG device.
18 ADCINB0 input ADC group B channel 0 analog input.
19 ADCINB1 input ADC group B channel 1 analog input.
20 ADCINB2/COMP1B/AIO10 input ADC group B channel 2 analog input, multiplexed with comparator 1B input and digital AIO10.
21 ADCINB3 input ADC group B channel 3 analog input.
22 ADCINB4/COMP2B/AIO12 input ADC group B channel 4 analog input, multiplexed with comparator 2B input and digital AIO12.
23 ADCINB6/COMP3B/AIO14 input ADC group B channel 6 analog input, multiplexed with comparator 3B input and digital AIO14.
24 ADCINB7 input ADC group B channel 7 analog input.
25 GPIO31/CANTXA bidirectional General-purpose I/O GPIO31 with CAN transmit output CANTXA as alternate function.
26 GPIO30/CANRXA bidirectional General-purpose I/O GPIO30 with CAN receive input CANRXA as alternate function.
27 GPIO29/SCITXDA/SCLA/TZ3 bidirectional General-purpose I/O GPIO29 with alternate functions SCI-A transmit output SCITXDA, open-drain I2C clock SCLA, and trip-zone input TZ3.
28 VSS power_in Digital ground pin.
29 VDDIO power_in Digital I/O buffer and flash supply; a single supply is used when VREG is enabled, and a decoupling capacitor is placed on each VDDIO pin.
30 TEST2 unconnected Test pin reserved for TI that must be left unconnected.
31 GPIO9/EPWM5B/LINTXA/HRCAP1 bidirectional General-purpose I/O GPIO9 with alternate functions ePWM5B output, LIN transmit LINTXA output, and high-resolution capture input HRCAP1.
32 GPIO28/SCIRXDA/SDAA/TZ2 bidirectional General-purpose I/O GPIO28 with alternate functions SCI-A receive input SCIRXDA, open-drain I2C data SDAA, and trip-zone input TZ2.
33 GPIO18/SPICLKA/LINTXA/XCLKOUT bidirectional General-purpose I/O GPIO18 with alternate functions SPI-A clock, LIN transmit output, and XCLKOUT (derived from SYSCLKOUT, equal to SYSCLKOUT/4 after reset).
34 GPIO17/SPISOMIA/TZ3 bidirectional General-purpose I/O GPIO17 with alternate functions SPI-A slave-out/master-in SPISOMIA and trip-zone input TZ3.
35 GPIO8/EPWM5A/ADCSOCAO bidirectional General-purpose I/O GPIO8 with alternate functions ePWM5A output (HRPWM channel) and ADC start-of-conversion output ADCSOCAO.
36 GPIO16/SPISIMOA/TZ2 bidirectional General-purpose I/O GPIO16 with alternate functions SPI-A slave-in/master-out SPISIMOA and trip-zone input TZ2.
37 GPIO12/TZ1/SCITXDA bidirectional General-purpose I/O GPIO12 with alternate functions trip-zone input TZ1 and SCI-A transmit output SCITXDA; the SPISIMOB alternate is not available on the PAG package.
38 GPIO7/EPWM4B/SCIRXDA bidirectional General-purpose I/O GPIO7 with alternate functions ePWM4B output and SCI-A receive input SCIRXDA.
39 GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO bidirectional General-purpose I/O GPIO6 with alternate functions ePWM4A output (HRPWM channel), external ePWM sync input EPWMSYNCI, and sync output EPWMSYNCO.
40 X2 output On-chip crystal oscillator output; a crystal or ceramic resonator must be connected between X1 and X2, and X2 must be left unconnected if unused.
41 X1 input 1.8 V on-chip crystal oscillator input that must not be driven with 3.3 V signals; if unused it must be connected to GND.
42 VSS power_in Digital ground pin.
43 VDD power_in CPU and logic digital supply; when the internal VREG is used, a 1.2 µF (minimum) capacitor must be placed between each VDD pin and ground.
44 GPIO19/XCLKIN/SPISTEA/LINRXA/ECAP1 bidirectional General-purpose I/O GPIO19 that also provides the XCLKIN external oscillator input path (not controlled by this pin's mux), with alternate functions SPI-A slave transmit enable SPISTEA, LIN receive LINRXA, and eCAP1 I/O.
45 GPIO38/TCK/XCLKIN bidirectional General-purpose I/O GPIO38 that serves as JTAG test clock TCK (internal pull-up) and external oscillator input XCLKIN; it is the default XCLKIN source and must not be used as a clock source during JTAG debug.
46 GPIO37/TDO bidirectional General-purpose I/O GPIO37 that serves as JTAG scan data output TDO with 8 mA drive.
47 GPIO35/TDI bidirectional General-purpose I/O GPIO35 that serves as JTAG test data input TDI with internal pull-up.
48 GPIO36/TMS bidirectional General-purpose I/O GPIO36 that serves as JTAG test mode select TMS with internal pull-up.
49 GPIO11/EPWM6B/LINRXA/HRCAP2 bidirectional General-purpose I/O GPIO11 with alternate functions ePWM6B output, LIN receive LINRXA, and high-resolution capture input HRCAP2.
50 GPIO5/EPWM3B/SPISIMOA/ECAP1 bidirectional General-purpose I/O GPIO5 with alternate functions ePWM3B output, SPI-A SPISIMOA, and eCAP1 I/O.
51 GPIO4/EPWM3A bidirectional General-purpose I/O GPIO4 with alternate function ePWM3A output (HRPWM channel).
52 GPIO10/EPWM6A/ADCSOCBO bidirectional General-purpose I/O GPIO10 with alternate functions ePWM6A output (HRPWM channel) and ADC start-of-conversion output ADCSOCBO.
53 GPIO3/EPWM2B/SPISOMIA/COMP2OUT bidirectional General-purpose I/O GPIO3 with alternate functions ePWM2B output, SPI-A SPISOMIA, and direct comparator 2 output COMP2OUT.
54 GPIO2/EPWM2A bidirectional General-purpose I/O GPIO2 with alternate function ePWM2A output (HRPWM channel).
55 GPIO1/EPWM1B/COMP1OUT bidirectional General-purpose I/O GPIO1 with alternate functions ePWM1B output and direct comparator 1 output COMP1OUT.
56 GPIO0/EPWM1A bidirectional General-purpose I/O GPIO0 with alternate function ePWM1A output (HRPWM channel).
57 VDDIO power_in Digital I/O buffer and flash supply; a single supply is used when VREG is enabled, and a decoupling capacitor is placed on each VDDIO pin.
58 VSS power_in Digital ground pin.
59 VDD power_in CPU and logic digital supply; when the internal VREG is used, a 1.2 µF (minimum) capacitor must be placed between each VDD pin and ground.
60 VREGENZ input Internal regulator enable with internal pull-down; connect directly to VSS to enable the internal 1.8 V VREG, or to VDDIO to disable it and use an external 1.8 V supply.
61 GPIO34/COMP2OUT/COMP3OUT bidirectional General-purpose I/O GPIO34 with alternate functions direct comparator outputs COMP2OUT and COMP3OUT; it may glitch during power-up when the on-chip VREG is used.
62 GPIO20/EQEP1A/COMP1OUT bidirectional General-purpose I/O GPIO20 with alternate functions EQEP1A input and direct comparator 1 output COMP1OUT.
63 GPIO21/EQEP1B/COMP2OUT bidirectional General-purpose I/O GPIO21 with alternate functions EQEP1B input and direct comparator 2 output COMP2OUT.
64 GPIO24/ECAP1 bidirectional General-purpose I/O GPIO24 with alternate function eCAP1 I/O; the SPISIMOB alternate is not available on the PAG package.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

CAD (KiCad official)

  • Symbol: TMS320F28034PAGS
  • Footprint: Package_QFP:TQFP-64_10x10mm_P0.5mm
  • 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: tms320f28034pags-etched.step / tms320f28034pags-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tms320f28034pags.step / tms320f28034pags.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (176 pp, sha256 cb9ccecfd6b5c484, retrieved 2026-10-11, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF