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TMS320F2802PZA-60

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Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TMS320F2802PZA-60

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

TMS320F2802PZA-60 from Texas Instruments, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GPIO12 bidirectional General-purpose input/output 12 (I/O/Z) with internal pullup, alternate functions: Trip Zone input 1 (I), SPI-B Slave in/Master out (I/O).
2 VSS power_in Digital ground pin.
3 VDDIO power_in Digital I/O Power Pin (3.3 V).
4 GPIO29 bidirectional General-purpose input/output 29 with 8-mA typical output buffer (I/O/Z) with internal pullup, alternate functions: SCI transmit data (O), Trip Zone 6 input (I).
5 GPIO33 bidirectional General-purpose input/output 33 (I/O/Z) with internal pullup, alternate functions: I2C clock open-drain bidirectional port (I/OD), Enhanced PWM external synch pulse output (O), ADC start-of-conversion (O).
6 GPIO30 bidirectional General-purpose input/output 30 with 8-mA typical output buffer (I/O/Z) with internal pullup, alternate function: Enhanced CAN-A receive data (I).
7 GPIO31 bidirectional General-purpose input/output 31 with 8-mA typical output buffer (I/O/Z) with internal pullup, alternate function: Enhanced CAN-A transmit data (O).
8 GPIO14 bidirectional General-purpose input/output 14 (I/O/Z) with internal pullup, alternate functions: Trip zone input 3 (I), SPI-B clock input/output (I/O).
9 GPIO15 bidirectional General-purpose input/output 15 (I/O/Z) with internal pullup, alternate functions: Trip zone input 4 (I), SPI-B slave transmit enable (I/O).
10 VDD power_in CPU and Logic Digital Power Pin (1.8 V).
11 VSS power_in Digital ground pin.
12 VDD1A18 power_in ADC Analog Power Pin (1.8 V).
13 VSS1AGND power_in ADC Analog Ground Pin.
14 VSSA2 power_in ADC Analog Ground Pin.
15 VDDA2 power_in ADC Analog Power Pin (3.3 V).
16 ADCINA7 input ADC Group A, Channel 7 input (I) for 0 to 3.0 V analog range.
17 ADCINA6 input ADC Group A, Channel 6 input (I) for 0 to 3.0 V analog range.
18 ADCINA5 input ADC Group A, Channel 5 input (I) for 0 to 3.0 V analog range.
19 ADCINA4 input ADC Group A, Channel 4 input (I) for 0 to 3.0 V analog range.
20 ADCINA3 input ADC Group A, Channel 3 input (I) for 0 to 3.0 V analog range.
21 ADCINA2 input ADC Group A, Channel 2 input (I) for 0 to 3.0 V analog range.
22 ADCINA1 input ADC Group A, Channel 1 input (I) for 0 to 3.0 V analog range.
23 ADCINA0 input ADC Group A, Channel 0 input (I) for 0 to 3.0 V analog range.
24 ADCLO input Low reference input, connect to analog ground (I).
25 VSSAIO power_in ADC Analog I/O Ground Pin.
26 VDDAIO power_in ADC Analog I/O Power Pin (3.3 V).
27 ADCINB0 input ADC Group B, Channel 0 input (I) for 0 to 3.0 V analog range.
28 ADCINB1 input ADC Group B, Channel 1 input (I) for 0 to 3.0 V analog range.
29 ADCINB2 input ADC Group B, Channel 2 input (I) for 0 to 3.0 V analog range.
30 ADCINB3 input ADC Group B, Channel 3 input (I) for 0 to 3.0 V analog range.
31 ADCINB4 input ADC Group B, Channel 4 input (I) for 0 to 3.0 V analog range.
32 ADCINB5 input ADC Group B, Channel 5 input (I) for 0 to 3.0 V analog range.
33 ADCINB6 input ADC Group B, Channel 6 input (I) for 0 to 3.0 V analog range.
34 ADCINB7 input ADC Group B, Channel 7 input (I) for 0 to 3.0 V analog range.
35 ADCREFIN input External reference input (I) for 1.024 V to 2.048 V precision source.
36 ADCREFM output Internal Reference Medium Output (O) requiring low ESR ceramic bypass capacitor of 2.2 μF to analog ground.
37 ADCREFP output Internal Reference Positive Output (O) requiring low ESR ceramic bypass capacitor of 2.2 μF to analog ground.
38 ADCRESEXT passive ADC External Current Bias Resistor connection point; connect 22-kΩ resistor to analog ground.
39 VSS2AGND power_in ADC Analog Ground Pin.
40 VDD2A18 power_in ADC Analog Power Pin (1.8 V).
41 VSS power_in Digital ground pin.
42 VDD power_in CPU and Logic Digital Power Pin (1.8 V).
43 GPIO34 bidirectional General-purpose input/output 34 (I/O/Z) with internal pullup.
44 GPIO1 bidirectional General-purpose input/output 1 (I/O/Z) with internal pullup disabled at reset, alternate function: Enhanced PWM1 Output B (O).
45 GPIO2 bidirectional General-purpose input/output 2 (I/O/Z) with internal pullup disabled at reset, alternate function: Enhanced PWM2 Output A and HRPWM channel (O).
46 VDDIO power_in Digital I/O Power Pin (3.3 V).
47 GPIO0 bidirectional General-purpose input/output 0 (I/O/Z) with internal pullup disabled at reset, alternate function: Enhanced PWM1 Output A and HRPWM channel (O).
48 GPIO3 bidirectional General-purpose input/output 3 (I/O/Z) with internal pullup disabled at reset, alternate function: Enhanced PWM2 Output B (O).
49 VSS power_in Digital ground pin.
50 GPIO16 bidirectional General-purpose input/output 16 (I/O/Z) with internal pullup, alternate functions: SPI-A slave in/master out (I/O), Trip zone input 5 (I).
51 GPIO4 bidirectional General-purpose input/output 4 (I/O/Z) with internal pullup disabled at reset, alternate function: Enhanced PWM3 output A and HRPWM channel (O).
52 GPIO17 bidirectional General-purpose input/output 17 (I/O/Z) with internal pullup, alternate functions: SPI-A slave out/master in (I/O), Trip zone input 6 (I).
53 GPIO5 bidirectional General-purpose input/output 5 (I/O/Z) with internal pullup disabled at reset, alternate functions: Enhanced PWM3 output B (O), Enhanced capture input/output 1 (I/O).
54 GPIO18 bidirectional General-purpose input/output 18 (I/O/Z) with internal pullup, alternate function: SPI-A clock input/output (I/O).
55 VSS power_in Digital ground pin.
56 GPIO6 bidirectional General-purpose input/output 6 (I/O/Z) with internal pullup disabled at reset, alternate functions: External ePWM sync pulse input (I), External ePWM sync pulse output (O).
57 GPIO19 bidirectional General-purpose input/output 19 (I/O/Z) with internal pullup, alternate function: SPI-A slave transmit enable input/output (I/O).
58 GPIO7 bidirectional General-purpose input/output 7 (I/O/Z) with internal pullup disabled at reset, alternate function: Enhanced capture input/output 2 (I/O).
59 VDD power_in CPU and Logic Digital Power Pin (1.8 V).
60 GPIO8 bidirectional General-purpose input/output 8 (I/O/Z) with internal pullup disabled at reset, alternate function: ADC start-of-conversion A (O).
61 GPIO9 bidirectional General-purpose input/output 9 (I/O/Z) with internal pullup disabled at reset, no peripheral functions available on F2802.
62 VSS power_in Digital ground pin.
63 GPIO20 bidirectional General-purpose input/output 20 (I/O/Z) with internal pullup, alternate function: Enhanced QEP1 input A (I).
64 GPIO10 bidirectional General-purpose input/output 10 (I/O/Z) with internal pullup disabled at reset, alternate function: ADC start-of-conversion B (O).
65 VDDIO power_in Digital I/O Power Pin (3.3 V).
66 XCLKOUT output Output clock (O/Z, 8 mA drive) derived from SYSCLKOUT at same frequency, one-half, or one-fourth of SYSCLKOUT; reset default = SYSCLKOUT/4; can be disabled by setting XCLKOUTDIV to 3.
67 GPIO21 bidirectional General-purpose input/output 21 (I/O/Z) with internal pullup, alternate function: Enhanced QEP1 input A (I).
68 VDD power_in CPU and Logic Digital Power Pin (1.8 V).
69 VSS power_in Digital ground pin.
70 GPIO11 bidirectional General-purpose input/output 11 (I/O/Z) with internal pullup, no peripheral functions available on F2802.
71 GPIO22 bidirectional General-purpose input/output 22 (I/O/Z) with internal pullup, alternate function: Enhanced QEP1 strobe (I/O).
72 GPIO23 bidirectional General-purpose input/output 23 (I/O/Z) with internal pullup, alternate function: Enhanced QEP1 index (I/O).
73 TDI input JTAG test data input (I, ↑) with internal pullup; clocked into selected register on rising edge of TCK.
74 TMS input JTAG test-mode select (I, ↑) with internal pullup; clocked into TAP controller on rising edge of TCK.
75 TCK input JTAG test clock (I, ↑) with internal pullup.
76 TDO output JTAG test data output (O/Z, 8 mA drive); contents of selected register shifted out on falling edge of TCK.
77 VSS power_in Digital ground pin.
78 XRS bidirectional Device Reset input and Watchdog Reset output (I/OD, ↑) with internal pullup; low level causes device to terminate execution and PC points to 0x3FFFC0; open-drain output for watchdog reset.
79 GPIO27 bidirectional General-purpose input/output 27 (I/O/Z) with internal pullup, alternate function: SPI-B slave transmit enable (I/O).
80 EMU0 bidirectional Emulator pin 0 (I/O/Z, 8 mA drive, ↑) with internal pullup; when TRST is driven high, used as interrupt to/from emulator system; external pullup resistor (2.2 kΩ to 4.7 kΩ) recommended.
81 EMU1 bidirectional Emulator pin 1 (I/O/Z, 8 mA drive, ↑) with internal pullup; when TRST is driven high, used as interrupt to/from emulator system; external pullup resistor (2.2 kΩ to 4.7 kΩ) recommended.
82 VDDIO power_in Digital I/O Power Pin (3.3 V).
83 GPIO24 bidirectional General-purpose input/output 24 (I/O/Z) with internal pullup, alternate functions: Enhanced capture 1 (I/O), SPI-B slave in/master out (I/O).
84 TRST input JTAG test reset (I, ↓) with internal pulldown; when driven high gives scan system control of device operations; must be maintained low during normal operation; external pulldown resistor (2.2 kΩ) required.
85 VDD power_in CPU and Logic Digital Power Pin (1.8 V).
86 X2 output Internal Oscillator Output (O) for crystal/resonator connected across X1 and X2; if not used must be left unconnected.
87 VSS power_in Digital ground pin.
88 X1 input Internal/External Oscillator Input (I) referenced to 1.8-V core digital power supply; crystal/resonator may be connected across X1 and X2; 1.8-V external oscillator may be connected with XCLKIN tied to GND.
89 VSS power_in Digital ground pin.
90 XCLKIN input External Oscillator Input (I) for 3.3-V external oscillator; tie X1 pin to GND when using external 3.3-V oscillator.
91 GPIO25 bidirectional General-purpose input/output 25 (I/O/Z) with internal pullup, alternate functions: Enhanced capture 2 (I/O), SPI-B master in/slave out (I/O).
92 GPIO28 bidirectional General-purpose input/output 28 with 8-mA typical output buffer (I/O/Z) with internal pullup, alternate functions: SCI receive data (I), Trip zone input 5 (I).
93 VDD power_in CPU and Logic Digital Power Pin (1.8 V).
94 VSS power_in Digital ground pin.
95 GPIO13 bidirectional General-purpose input/output 13 (I/O/Z) with internal pullup, alternate functions: Trip zone input 2 (I), SPI-B slave out/master in (I/O).
96 VDD3VFL power_in 3.3-V Flash Core Power Pin; must be connected to 3.3 V at all times.
97 TEST1 input Test Pin reserved for TI; must be left unconnected.
98 TEST2 input Test Pin reserved for TI; must be left unconnected.
99 GPIO26 bidirectional General-purpose input/output 26 (I/O/Z) with internal pullup, alternate function: SPI-B clock (I/O).
100 GPIO32 bidirectional General-purpose input/output 32 (I/O/Z) with internal pullup, alternate functions: I2C data open-drain bidirectional port (I/OD), Enhanced PWM external sync pulse input (I), ADC start-of-conversion (O).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

CAD (KiCad official)

  • Symbol: TMS320F2802PZA-60
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: tms320f2802pza-60-etched.step / tms320f2802pza-60-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tms320f2802pza-60.step / tms320f2802pza-60.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (157 pp, sha256 a13113c4c002c567, retrieved 2026-10-07, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF