# TMN2012S

**Tritech MOS** · MOSFETs · SOP-8

TMN2012S from Tritech MOS, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source of the N-channel MOSFET (pin 1), with continuous source current IS up to 10A. |
| 2 | S | passive | Source of the N-channel MOSFET, with continuous source current IS up to 10A. |
| 3 | S | passive | Source of the N-channel MOSFET, with continuous source current IS up to 10A. |
| 4 | G | input | Gate of the N-channel MOSFET, with gate-source voltage rated at ±12V maximum. |
| 5 | D | passive | Drain of the N-channel MOSFET, rated for 20V drain-source voltage and 10A continuous drain current. |
| 6 | D | passive | Drain of the N-channel MOSFET, rated for 20V drain-source voltage and 10A continuous drain current. |
| 7 | D | passive | Drain of the N-channel MOSFET, rated for 20V drain-source voltage and 10A continuous drain current. |
| 8 | D | passive | Drain of the N-channel MOSFET, rated for 20V drain-source voltage and 10A continuous drain current. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Tritech MOS |
| Package | SOP-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage | VDS |  |  | 20 | V |  | 1 |
| Gate-Source Voltage | VGS | -12 |  | 12 | V |  | 1 |
| Continuous Drain Current | ID |  |  | 10 | A | TA= 25°C | 1 |
| Pulsed Drain Current | IDM |  |  | 20 | A |  | 1 |
| Power Dissipation | PD |  |  | 2.25 | W | TA= 25°C | 1 |
| Operating Junction and Storage Temperature Range | TJ, TSTG | -55 |  | 150 | °C |  | 1 |
| Thermal Resistance from Junction to Ambient | RθJA |  | 90 |  | °C/W | Surface mounted on 1 inch² FR-4 board with 2OZ copper | 1 |
| Drain-Source Breakdown Voltage | BVDSS | 20 |  |  | V | VGS = 0 V, ID = 250µA | 2 |
| Gate Leakage Current | IGSS | -100 |  | 100 | nA | VGS = ±12V, VDS = 0 V | 2 |
| Drain Cut-off Current | IDSS |  |  | 1 | µA | VDS = 20V, VGS = 0 V | 2 |
| Gate Threshold Voltage | VGS(th) | 0.45 | 0.7 | 1 | V | VGS = VDS, ID = 250µA | 2 |
| Drain-Source On-State Resistance | RDS(on) |  | 12 | 15 | mΩ | VGS = 4.5V, ID = 5A | 2 |
| Drain-Source On-State Resistance | RDS(on) |  | 17 | 21 | mΩ | VGS = 2.5V, ID = 4.7A | 2 |
| Drain-Source On-State Resistance | RDS(on) |  | 28 | 50 | mΩ | VGS = 1.8V, ID = 4.3A | 2 |
| Body Diode Voltage | VSD |  |  | 1.2 | V | IS=4A, VGS = 0V | 2 |
| Continuous Source Current | IS |  |  | 10 | A |  | 2 |

## CAD (KiCad official)

- Symbol: `TMN2012S`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `tmn2012s-etched.step` / `tmn2012s-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tmn2012s.step` / `tmn2012s.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Tritech MOS datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590906754375241728) (5 pp, sha256 `a6b72ec6a230400c`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tmn2012s-datasheet.pdf)