TM4050GD from Tritech-MOS, in a TO-252-4L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	S1	passive	Source of the N-channel MOSFET (40V, 50A, RDS(ON) 4.2mΩ typ. at VGS=10V); marked as PIN1 in the package drawing.
2	G1	input	Gate of the N-channel MOSFET, with VGS rated ±20V and threshold of 1V min to 2.5V max.
3	S2	passive	Source of the P-channel MOSFET (-40V, -50A, RDS(ON) 11.5mΩ typ. at VGS=-10V).
4	G2	input	Gate of the P-channel MOSFET, with VGS rated ±20V and threshold of -1V min to -2.5V max.
5	D1/D2	passive	Common drain of both the N-channel and P-channel MOSFETs, connected to the exposed tab (drain tab).

Key specifications

Parameter	Value
Manufacturer	Tritech-MOS
Package	TO-252-4L
Category	Transistors/Thyristors
Pins	5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Drain-Source Voltage (N-CH)	VDS			40	V		1
Drain-Source Voltage (P-CH)	VDS	-40			V		1
Gate-Source Voltage (N-CH)	VGS	-20		20	V		1
Gate-Source Voltage (P-CH)	VGS	-20		20	V		1
Continuous Drain Current (N-CH)	ID			50	A	TC=25℃	1
Continuous Drain Current (P-CH)	ID	-50			A	TC=25℃	1
Continuous Drain Current (N-CH)	ID			35	A	TC=100℃	1
Continuous Drain Current (P-CH)	ID	-20			A	TC=100℃	1
Pulsed Drain Current (N-CH)				250	A		1
Pulsed Drain Current (P-CH)		-130			A		1
Power Dissipation (N-CH)	PD			55	W	TC=25℃	1
Power Dissipation (P-CH)	PD			55	W	TC=25℃	1
Operating and Storage Junction Temperature Range	TJ, TSTG	-55		150	℃		1
Thermal Resistance, Junction to Case	RθJC			2.3	℃/W		1
Thermal Resistance, Junction to Ambient	RθJA			62	℃/W		1
Drain-Source Breakdown Voltage (N-CH)	BVDSS	40			V	VGS=0V,ID=250μA	2
Zero Gate Voltage Drain Current (N-CH)	IDSS			1	μA	VGS=0V, VDS=-40V	2
Gate-Source Leakage Current (N-CH)	IGSS	-100		100	nA	VGS=±20V, VDS=0A	2
Gate-Source Threshold Voltage (N-CH)	VGS(th)	1	1.6	2.5	V	VGS=VDS, ID=250μA	2
Drain-Source On Resistance (N-CH)	RDS(ON)		4.2	5.5	mΩ	VGS=10V,ID=20A	2
Drain-Source On Resistance (N-CH)	RDS(ON)		5.3	7	mΩ	VGS=4.5V,ID=10A	2
Input Capacitance (N-CH)	Ciss		2380	3400	pF	VDS=25V, VGS=0V, f=1MHz	2
Output Capacitance (N-CH)	Coss		230	385	pF	VDS=25V, VGS=0V, f=1MHz	2
Reverse Transfer Capacitance (N-CH)	Crss		148	210	pF	VDS=25V, VGS=0V, f=1MHz	2
Turn-On Delay Time (N-CH)	td(on)		14.2	28	ns	VDD=20V, ID=1A, RGEN=3.3Ω, VGS=10V	2
Rise Time (N-CH)	tr		18.3	36	ns	VDD=20V, ID=1A, RGEN=3.3Ω, VGS=10V	2
Turn-Off Delay Time (N-CH)	td(off)		38.8	76	ns	VDD=20V, ID=1A, RGEN=3.3Ω, VGS=10V	2
Fall Time (N-CH)	tf		13.9	28	ns	VDD=20V, ID=1A, RGEN=3.3Ω, VGS=10V	2
Total Gate Charge (N-CH)	Qg		25	50	nC	VGS=4.5V, VDS=32V, ID=10A	2
Gate-Source Charge (N-CH)	Qgs		6.5	13	nC	VGS=4.5V, VDS=32V, ID=10A	2
Gate-Drain Miller Charge (N-CH)	Qgd		12.1	24	nC	VGS=4.5V, VDS=32V, ID=10A	2
Drain Diode Forward Voltage (N-CH)	VSD			1	V	VGS=0V,IS=1A	2
Continuous Source Current (N-CH)	LS			50	A	VG=VD=0V , Force Current	2
Pulsed Source Current (N-CH)	lsm			160	A		2
Drain-Source Breakdown Voltage (P-CH)	BVDSS	-40			V	VGS=0V,ID=250μA	5
Zero Gate Voltage Drain Current (P-CH)	IDSS			-1	μA	VGS=0V, VDS=-40V,TJ=25℃	5
Gate-Source Leakage Current (P-CH)	IGSS	-100		100	nA	VGS=±20V, VDS=0A	5
Gate-Source Threshold Voltage (P-CH)	VGS(th)	-1	-1.6	-2.5	V	VGS=VDS, ID=250μA	5
Drain-Source On Resistance (P-CH)	RDS(ON)		11.5	15	mΩ	VGS=-10V,ID=-10A	5
Drain-Source On Resistance (P-CH)	RDS(ON)		16	22	mΩ	VGS=-4.5V,ID=-8A	5
Input Capacitance (P-CH)	Ciss		2557	3800	pF	VDS=-25V, VGS=0V, f=1MHz	5
Output Capacitance (P-CH)	Coss		220	320	pF	VDS=-25V, VGS=0V, f=1MHz	5
Reverse Transfer Capacitance (P-CH)	Crss		127	180	pF	VDS=-25V, VGS=0V, f=1MHz	5
Turn-On Delay Time (P-CH)	td(on)		23	40	ns	VDD=-20V, ID=-1A, RG=6Ω, VGS=-10V	5
Rise Time (P-CH)	tr		10	20	ns	VDD=-20V, ID=-1A, RG=6Ω, VGS=-10V	5
Turn-Off Delay Time (P-CH)	td(off)		135	250	ns	VDD=-20V, ID=-1A, RG=6Ω, VGS=-10V	5
Fall Time (P-CH)	tf		46	90	ns	VDD=-20V, ID=-1A, RG=6Ω, VGS=-10V	5
Total Gate Charge (P-CH)	Qg		22.2	40	nC	VGS=-4.5V, VDS=-32V, ID=-10A	5
Gate-Source Charge (P-CH)	Qgs		8.2	16	nC		5
Gate-Drain Miller Charge (P-CH)	Qgd		8.8	16	nC		5
Source Drain Diode Forward Voltage (P-CH)	VSD			-1	V	VGS=0V,IS=-1A,TJ=25℃	5

CAD (KiCad official)

Symbol: TM4050GD
Footprint: Package_TO_SOT_SMD:TO-252-4
3D model: TO-252-4L (KiCad packages3D, STEP)
3D model files: tm4050gd-etched.step / tm4050gd-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tm4050gd.step / tm4050gd.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Tritech-MOS datasheet (8 pp, sha256 33f845a4e41556c6, retrieved 2026-11-05, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

TM4050GD

Verified TM4050GD

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3D Model

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