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TM10N10S

Public Made by Adom

by adom

Tritech-MOS MOSFETs, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs Publish 0.1.0 · Ray 12d ago
viewers tm10n10s: viewers · Ray 12d ago
package.json Publish 0.1.0 · Ray 12d ago
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README.md Publish 0.1.0 · Ray 12d ago
tm10n10s-etched.glb Publish 0.1.0 · Ray 12d ago
tm10n10s-etched.step tm10n10s: factory component page (tier=lcsc) · Ray 12d ago
tm10n10s-hero.glb tm10n10s: hero GLB from the etched model (keeps the MPN mark) · Ray 12d ago
tm10n10s-hero.overlay.json Publish 0.1.0 · Ray 12d ago
tm10n10s.glb Publish 0.1.0 · Ray 12d ago
tm10n10s.kicad_mod Publish 0.1.0 · Ray 12d ago
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TM10N10S

Tritech-MOS · MOSFETs · SOP-8

TM10N10S from Tritech-MOS, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S passive Source terminal of the N-channel MOSFET, connected in parallel with pins 2 and 3 and shown at PIN1 on the package diagram.
2 S passive Source terminal of the N-channel MOSFET, connected in parallel with pins 1 and 3.
3 S passive Source terminal of the N-channel MOSFET, connected in parallel with pins 1 and 2.
4 G input Gate terminal of the N-channel MOSFET with a maximum gate-source voltage of ±20 V and a typical gate threshold voltage of 1.5 V (1.0 V min to 2.5 V max).
5 D passive Drain terminal of the MOSFET, connected in parallel with pins 6, 7 and 8, rated for a maximum drain-source voltage of 100 V and a continuous drain current of 10 A.
6 D passive Drain terminal of the MOSFET, connected in parallel with pins 5, 7 and 8, rated for a maximum drain-source voltage of 100 V.
7 D passive Drain terminal of the MOSFET, connected in parallel with pins 5, 6 and 8, rated for a maximum drain-source voltage of 100 V.
8 D passive Drain terminal of the MOSFET, connected in parallel with pins 5, 6 and 7, rated for a maximum drain-source voltage of 100 V.

Key specifications

Parameter Value
Manufacturer Tritech-MOS
Package SOP-8
Category Transistors/Thyristors
Pins 8

CAD (KiCad official)

  • Symbol: TM10N10S
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: tm10n10s-etched.step / tm10n10s-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tm10n10s.step / tm10n10s.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Tritech-MOS datasheet (7 pp, sha256 12b4899bdaa1df25, retrieved 2026-10-28, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF