# TLV5620IDR

**Texas Instruments** · Digital To Analog Converters (DAC) · SOP-14

TLV5620IDR from Texas Instruments, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground return and reference terminal for the device. |
| 2 | REFA | input | Reference voltage input to DAC A, which defines the output analog range. |
| 3 | REFB | input | Reference voltage input to DAC B, which defines the analog output range. |
| 4 | REFC | input | Reference voltage input to DAC C, which defines the analog output range. |
| 5 | REFD | input | Reference voltage input to DAC D, which defines the analog output range. |
| 6 | DATA | input | Serial interface digital data input, with each data bit clocked into the serial register on the falling edge of CLK. |
| 7 | CLK | input | Serial interface clock; input digital data is shifted into the serial interface register on the falling edge of CLK. |
| 8 | LOAD | input | Serial interface load control; when LDAC is low, the falling edge of LOAD latches the data into the output latch and immediately produces the analog output voltage. |
| 9 | DACD | output | DAC D analog output. |
| 10 | DACC | output | DAC C analog output. |
| 11 | DACB | output | DAC B analog output. |
| 12 | DACA | output | DAC A analog output. |
| 13 | LDAC | input | Load DAC; when high, no DAC output updates occur during serial input, and the DAC outputs update only when LDAC is taken from high to low. |
| 14 | VDD | power_in | Positive supply voltage; the recommended supply range is 2.7 V to 5.25 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOP-14 |
| Category | Data Acquisition |
| Pins | 14 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VDD |  |  | 7 | V | VDD, GND | 7 |
| Storage temperature range | Tstg | -50 |  | 150 | °C |  | 7 |
| Lead temperature |  |  |  | 260 | °C | 1,6 mm (1/16 inch) from case for 10 seconds | 7 |
| Supply voltage | VDD | 2.7 | 3.3 | 5.25 | V |  | 7 |
| Low-level input voltage | VIL |  |  | 0.8 | V |  | 7 |
| Load resistance | RL | 10 |  |  | kΩ |  | 7 |
| Setup time, data input | tsu(DATA-CLK) | 50 |  |  | ns | see Figures 1 and 2 | 7 |
| Valid time, data input valid after CLK↓ | tv(DATA-CLK) | 50 |  |  | ns | see Figures 1 and 2 | 7 |
| Setup time, CLK eleventh falling edge to LOAD | tsu(CLK-LOAD) | 50 |  |  | ns | see Figure 1 | 7 |
| Setup time, LOAD↑ to CLK↓ | tsu(LOAD-CLK) | 50 |  |  | ns | see Figure 1 | 7 |
| Pulse duration, LOAD | tw(LOAD) | 250 |  |  | ns | see Figure 1 | 7 |
| Pulse duration, LDAC | tw(LDAC) | 250 |  |  | ns | see Figure 2 | 7 |
| Setup time, LOAD↑ to LDAC↓ | tsu(LOAD-LDAC) | 0 |  |  | ns | see Figure 2 | 7 |
| CLK frequency |  |  |  | 1 | MHz |  | 7 |
| Operating free-air temperature TLV5620I | TA | -40 |  | 85 | °C | TLV5620I | 7 |
| Operating free-air temperature range TLV5620I | TA | -40 |  | 85 | °C | TLV5620I | 7 |
| High-level input current | IIH | -10 |  | 10 | µA | VI = VDD | 8 |
| Low-level input current | IIL | -10 |  | 10 | µA | VI = 0 V | 8 |
| Output sink current | IO(sink) | 20 |  |  | µA | Each DAC output | 8 |
| Output source current | IO(source) | 1 |  |  | mA | Each DAC output | 8 |
| Input capacitance | Ci |  |  | 15 | pF |  | 8 |
| Reference input capacitance | Ci |  |  | 15 | pF |  | 8 |
| Supply current | IDD |  |  | 2 | mA | VDD = 3.3 V | 8 |
| Reference input current | Iref | -10 |  | 10 | µA | VDD = 3.3 V, Vref = 1.5 V | 8 |
| Linearity error (end point corrected) | EL | -1 |  | 1 | LSB | Vref = 1.25 V, × 2 gain, See Note 1 | 8 |
| Differential linearity error | ED | -0.9 |  | 0.9 | LSB | Vref = 1.25 V, × 2 gain, See Note 2 | 8 |
| Zero-scale error | EZS | 0 |  | 30 | mV | Vref = 1.25 V, × 2 gain, See Note 3 | 8 |
| Zero-scale error temperature coefficient |  |  |  | 10 | µV/°C | Vref = 1.25 V, × 2 gain, See Note 4 | 8 |
| Full-scale error | EFS | -60 |  | 60 | mV | Vref = 1.25 V, × 2 gain, See Note 5 | 8 |
| Full-scale error temperature coefficient |  | -25 |  | 25 | µV/°C | Vref = 1.25 V, × 2 gain, See Note 6 | 8 |
| Power-supply sensitivity | PSRR |  |  | 0.5 | mV/V | See Notes 7 and 8 | 8 |
| Output slew rate |  | 1 |  |  | V/µs | CL = 100 pF RL = 10 kΩ | 8 |
| Output settling time |  |  |  | 10 | µs | To ±0.5 LSB, CL = 100 pF, RL = 10 kΩ, See Note 9 | 8 |
| Large-signal bandwidth |  |  |  | 100 | kHz | Measured at -3 dB point | 8 |
| Digital crosstalk |  |  |  | -50 | dB | CLK = 1-MHz square wave measured at DACA-DACD | 8 |
| Reference feedthrough |  |  |  | -60 | dB | See Note 10 | 8 |
| Channel-to-channel isolation |  |  |  | -60 | dB | See Note 11 | 8 |
| Reference input bandwidth |  |  |  | 100 | kHz | See Note 12 | 8 |

## CAD (KiCad official)

- Symbol: `TLV5620IDR`
- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`
- 3D model: SOP-14 (KiCad packages3D, STEP)
- 3D model files: `tlv5620idr-etched.step` / `tlv5620idr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tlv5620idr.step` / `tlv5620idr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/tlv5620.pdf) (17 pp, sha256 `7e1717b3cf48348b`, retrieved 2026-11-05, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tlv5620idr-datasheet.pdf)