TLV5619CPWR

{
  "slug": "tlv5619cpwr",
  "version": "0.1.0",
  "type": "component",
  "description": "Texas Instruments Digital To Analog Converters (DAC), TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "data acquisition",
    "tlv5619cpwr",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "tlv5619cpwr.kicad_sym",
    "tlv5619cpwr.kicad_mod",
    "tlv5619cpwr.glb",
    "tlv5619cpwr.step",
    "tlv5619cpwr.lbr",
    "docs/hero.png",
    "docs/tlv5619cpwr-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "tlv5619cpwr-hero.glb",
    "tlv5619cpwr-hero.overlay.json"
  ],
  "component": {
    "mpn": "TLV5619CPWR",
    "manufacturer": "Texas Instruments",
    "package": "TSSOP-20",
    "pin_count": 20,
    "category": "Data Acquisition",
    "subcategory": "Digital To Analog Converters (DAC)",
    "datasheet": "https://www.ti.com/cn/lit/gpn/tlv5619",
    "parts": {
      "symbol": "tlv5619cpwr.kicad_sym",
      "footprint": "tlv5619cpwr.kicad_mod",
      "model_3d": "tlv5619cpwr-hero.glb",
      "model_3d_plain": "tlv5619cpwr.glb",
      "model_3d_step": "tlv5619cpwr-etched.step",
      "model_3d_step_plain": "tlv5619cpwr.step",
      "lbr": "tlv5619cpwr.lbr"
    },
    "distributor_links": {
      "lcsc": "C2679843",
      "digikey": "TLV5619CPWR-ND",
      "mouser": "595-TLV5619CPWR"
    },
    "distributor_check": {
      "checked_at": "2026-10-08T23:07:04Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "TLV5619CPWR-ND",
        "status": "found",
        "lifecycle": "Active"
      },
      "mouser": {
        "pn": "595-TLV5619CPWR",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "D2",
        "type": "input",
        "description": "Parallel data input bit D2 of the 12-bit DAC code (D0 is LSB, D11 is MSB), latched on the positive edge of WE while CS is low."
      },
      {
        "number": "2",
        "name": "D3",
        "type": "input",
        "description": "Parallel data input bit D3 of the 12-bit DAC code, latched on the positive edge of WE while CS is low."
      },
      {
        "number": "3",
        "name": "D4",
        "type": "input",
        "description": "Parallel data input bit D4 of the 12-bit DAC code, latched on the positive edge of WE while CS is low."
      },
      {
        "number": "4",
        "name": "D5",
        "type": "input",
        "description": "Parallel data input bit D5 of the 12-bit DAC code, latched on the positive edge of WE while CS is low."
      },
      {
        "number": "5",
        "name": "D6",
        "type": "input",
        "description": "Parallel data input bit D6 of the 12-bit DAC code, latched on the positive edge of WE while CS is low."
      },
      {
        "number": "6",
        "name": "D7",
        "type": "input",
        "description": "Parallel data input bit D7 of the 12-bit DAC code, latched on the positive edge of WE while CS is low."
      },
      {
        "number": "7",
        "name": "D8",
        "type": "input",
        "description": "Parallel data input bit D8 of the 12-bit DAC code, latched on the positive edge of WE while CS is low."
      },
      {
        "number": "8",
        "name": "D9",
        "type": "input",
        "description": "Parallel data input bit D9 of the 12-bit DAC code, latched on the positive edge of WE while CS is low."
      },
      {
        "number": "9",
        "name": "D10",
        "type": "input",
        "description": "Parallel data input bit D10 of the 12-bit DAC code, latched on the positive edge of WE while CS is low."
      },
      {
        "number": "10",
        "name": "D11",
        "type": "input",
        "description": "Parallel data input bit D11 (MSB) of the 12-bit DAC code, latched on the positive edge of WE while CS is low."
      },
      {
        "number": "11",
        "name": "VDD",
        "type": "power_in",
        "description": "Positive power supply, specified at 4.5 V to 5.5 V for 5-V operation or 2.7 V to 3.3 V for 3-V operation, with absolute maximum of 7 V."
      },
      {
        "number": "12",
        "name": "REFIN",
        "type": "input",
        "description": "Voltage reference input, specified from 0 to VDD - 1.5 V (2.048 V nominal at 5 V, 1.024 V nominal at 3 V); reference inputs above VDD/2 cause output saturation at large codes."
      },
      {
        "number": "13",
        "name": "OUT",
        "type": "output",
        "description": "Rail-to-rail buffered analog voltage output, driving loads of at least 2 kΩ and up to 100 pF capacitance."
      },
      {
        "number": "14",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference for the supply and all digital and analog signals."
      },
      {
        "number": "15",
        "name": "PD",
        "type": "input",
        "description": "Power-down control; when low, disables all buffer amplifier voltages to reduce supply current (device power-down mode, about 50 nW)."
      },
      {
        "number": "16",
        "name": "LDAC",
        "type": "input",
        "description": "Load DAC control; a low level transfers the data in the holding latch to the DAC output asynchronously, and it can be held low for continuous update."
      },
      {
        "number": "17",
        "name": "WE",
        "type": "input",
        "description": "Write enable; the data bus is latched on the positive edge of WE, which requires CS to be low."
      },
      {
        "number": "18",
        "name": "CS",
        "type": "input",
        "description": "Chip select; the device is enabled for writes only when CS is low, with CS low required before the positive WE edge (13 ns minimum setup)."
      },
      {
        "number": "19",
        "name": "D0",
        "type": "input",
        "description": "Parallel data input bit D0 (LSB) of the 12-bit DAC code, latched on the positive edge of WE while CS is low."
      },
      {
        "number": "20",
        "name": "D1",
        "type": "input",
        "description": "Parallel data input bit D1 of the 12-bit DAC code, latched on the positive edge of WE while CS is low."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The datasheet gives one terminal table and one pin-out drawing shared by the DW (SOIC) and PW (TSSOP; Pin descriptions for D0-D11, CS, WE and LDAC are paraphrased from the timing and interface sections "
        ],
        "pages_sent": 27,
        "cost_usd": 0.0967,
        "at": "2026-10-08T23:06:03"
      },
      "datasheet": {
        "url": "https://www.ti.com/cn/lit/gpn/tlv5619",
        "pages": 27,
        "sha256": "31589d577aa88ec8",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 20,
        "described": 20,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "tlv5619cpwr.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.4,
          6.5,
          1.2
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "97339947f3a7196470ec2f1d9f9b92bb2fc2ab66ad53be0cf105192585ef3c9a",
        "checked": "2026-10-08",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "tlv5619cpwr-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.4,
          6.5,
          1.2
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "daeb9bbd6f8410551debcae5d5fee732a88d2b2af0d60af5fa73b0876f29aabc",
        "checked": "2026-10-08",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}