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TLV5619CPWR

Public Made by Adom

by adom

Texas Instruments Digital To Analog Converters (DAC), TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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TLV5619CPWR

Texas Instruments · Digital To Analog Converters (DAC) · TSSOP-20

TLV5619CPWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 D2 input Parallel data input bit D2 of the 12-bit DAC code (D0 is LSB, D11 is MSB), latched on the positive edge of WE while CS is low.
2 D3 input Parallel data input bit D3 of the 12-bit DAC code, latched on the positive edge of WE while CS is low.
3 D4 input Parallel data input bit D4 of the 12-bit DAC code, latched on the positive edge of WE while CS is low.
4 D5 input Parallel data input bit D5 of the 12-bit DAC code, latched on the positive edge of WE while CS is low.
5 D6 input Parallel data input bit D6 of the 12-bit DAC code, latched on the positive edge of WE while CS is low.
6 D7 input Parallel data input bit D7 of the 12-bit DAC code, latched on the positive edge of WE while CS is low.
7 D8 input Parallel data input bit D8 of the 12-bit DAC code, latched on the positive edge of WE while CS is low.
8 D9 input Parallel data input bit D9 of the 12-bit DAC code, latched on the positive edge of WE while CS is low.
9 D10 input Parallel data input bit D10 of the 12-bit DAC code, latched on the positive edge of WE while CS is low.
10 D11 input Parallel data input bit D11 (MSB) of the 12-bit DAC code, latched on the positive edge of WE while CS is low.
11 VDD power_in Positive power supply, specified at 4.5 V to 5.5 V for 5-V operation or 2.7 V to 3.3 V for 3-V operation, with absolute maximum of 7 V.
12 REFIN input Voltage reference input, specified from 0 to VDD - 1.5 V (2.048 V nominal at 5 V, 1.024 V nominal at 3 V); reference inputs above VDD/2 cause output saturation at large codes.
13 OUT output Rail-to-rail buffered analog voltage output, driving loads of at least 2 kΩ and up to 100 pF capacitance.
14 GND power_in Ground reference for the supply and all digital and analog signals.
15 PD input Power-down control; when low, disables all buffer amplifier voltages to reduce supply current (device power-down mode, about 50 nW).
16 LDAC input Load DAC control; a low level transfers the data in the holding latch to the DAC output asynchronously, and it can be held low for continuous update.
17 WE input Write enable; the data bus is latched on the positive edge of WE, which requires CS to be low.
18 CS input Chip select; the device is enabled for writes only when CS is low, with CS low required before the positive WE edge (13 ns minimum setup).
19 D0 input Parallel data input bit D0 (LSB) of the 12-bit DAC code, latched on the positive edge of WE while CS is low.
20 D1 input Parallel data input bit D1 of the 12-bit DAC code, latched on the positive edge of WE while CS is low.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Data Acquisition
Pins 20

CAD (KiCad official)

  • Symbol: TLV5619CPWR
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: tlv5619cpwr-etched.step / tlv5619cpwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlv5619cpwr.step / tlv5619cpwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (27 pp, sha256 31589d577aa88ec8, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF