component

TLV2548QDW

Public Made by Adom

by adom

Texas Instruments Analog To Digital Converters (ADC), SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentdata acquisitiontlv2548qdwfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 15d ago
viewers tlv2548qdw: viewers · Ray 15d ago
package.json Publish 0.1.0 · Ray 15d ago
page.json Set visibility: public · Ray 15d ago
README.md Publish 0.1.0 · Ray 15d ago
tlv2548qdw-etched.glb tlv2548qdw: factory component page (tier=lcsc) · Ray 15d ago
tlv2548qdw-etched.step tlv2548qdw: factory component page (tier=lcsc) · Ray 15d ago
tlv2548qdw-hero.glb tlv2548qdw: hero GLB from the etched model (keeps the MPN mark) · Ray 15d ago
tlv2548qdw-hero.overlay.json Publish 0.1.0 · Ray 15d ago
tlv2548qdw.glb Publish 0.1.0 · Ray 15d ago
tlv2548qdw.kicad_mod Publish 0.1.0 · Ray 15d ago
tlv2548qdw.kicad_sym Publish 0.1.0 · Ray 15d ago
tlv2548qdw.lbr Publish 0.1.0 · Ray 15d ago
tlv2548qdw.step Publish 0.1.0 · Ray 15d ago

TLV2548QDW

Texas Instruments · Analog To Digital Converters (ADC) · SOIC-20-300mil

TLV2548QDW from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SDO tri_state The 3-state serial output carries the A/D conversion result MSB (D15) first and stays high-impedance while CS is high and until the MSB is presented.
2 SDI input Serial data input takes the MSB (D15) first, with the 4-bit command in D(15-12) and up to 12 bits of configuration data, latched on SCLK rising edges after CS falls (or falling edges when FS is used).
3 SCLK input Input serial clock from the host clocks SDI into the input register and may serve as the conversion clock source; the device supports CPOL = 0 and SCLK up to 20 MHz.
4 EOC/(INT) output Programmed as EOC, it goes low at the end of the sampling period until conversion data are ready (conversion mode 00 only); programmed as INT, its falling edge indicates data ready and is cleared by the following CS↓ or FS.
5 VCC power_in Positive supply voltage; the device operates from a single 3-V to 5.5-V supply.
6 A0 input Analog signal input multiplexed internally; the driving source impedance should be less than or equal to 1 kΩ, otherwise use CSTART or long sampling.
7 A1 input Analog signal input multiplexed internally; the driving source impedance should be less than or equal to 1 kΩ, otherwise use CSTART or long sampling.
8 A2 input Analog signal input multiplexed internally; the driving source impedance should be less than or equal to 1 kΩ, otherwise use CSTART or long sampling.
9 A3 input Analog signal input multiplexed internally; the driving source impedance should be less than or equal to 1 kΩ, otherwise use CSTART or long sampling.
10 A4 input Analog signal input multiplexed internally; the driving source impedance should be less than or equal to 1 kΩ, otherwise use CSTART or long sampling.
11 A5 input Analog signal input multiplexed internally; the driving source impedance should be less than or equal to 1 kΩ, otherwise use CSTART or long sampling.
12 A6 input Analog signal input multiplexed internally; the driving source impedance should be less than or equal to 1 kΩ, otherwise use CSTART or long sampling.
13 A7 input Analog signal input multiplexed internally; the driving source impedance should be less than or equal to 1 kΩ, otherwise use CSTART or long sampling.
14 CSTART input Controls the start and length of sampling for extended sampling: the falling edge starts sampling and the rising edge (with CS high) starts conversion; tie to VCC if not used.
15 GND power_in Ground return for the internal circuitry; all voltage measurements are referenced to GND.
16 PWDN input When held at logic zero, both the analog and reference circuits are powered down; the device restarts via an active CS, FS or CSTART after this pin returns to logic one.
17 FS input DSP frame sync input that marks the start of a serial frame; a high-to-low transition resets the 4-bit counter and enables SDI, and it should be tied to VCC if not used.
18 REFM input External reference input or internal reference decoupling; the code 000h corresponds to VREFM.
19 REFP input External reference input or internal reference decoupling; the maximum input range is the difference between REFP and REFM, with 10 µF and 0.1 µF shunt capacitors between REFP and REFM.
20 CS input Chip select: a high-to-low transition resets the 4-bit counter, enables SDI and releases SDO from 3-state, and CS edges must occur while SCLK is low for SPI use.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-20-300mil
Category Data Acquisition
Pins 20

CAD (KiCad official)

  • Symbol: TLV2548QDW
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
  • 3D model files: tlv2548qdw-etched.step / tlv2548qdw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlv2548qdw.step / tlv2548qdw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (44 pp, sha256 7ec6c3c44c39e2be, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF