TLV1544CPWR

{
  "slug": "tlv1544cpwr",
  "version": "0.1.0",
  "type": "component",
  "description": "Texas Instruments Analog To Digital Converters (ADC), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
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    "data acquisition",
    "tlv1544cpwr",
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  "component": {
    "mpn": "TLV1544CPWR",
    "manufacturer": "Texas Instruments",
    "package": "TSSOP-16",
    "pin_count": 16,
    "category": "Data Acquisition",
    "subcategory": "Analog To Digital Converters (ADC)",
    "datasheet": "https://www.ti.com/cn/lit/gpn/tlv1544",
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    "distributor_links": {
      "lcsc": "C2670268",
      "digikey": "TLV1544CPWR-ND",
      "mouser": "595-TLV1544CPWR"
    },
    "distributor_check": {
      "checked_at": "2026-10-11T09:03:03Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "TLV1544CPWR-ND",
        "status": "found",
        "lifecycle": "Active"
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      "mouser": {
        "pn": "595-TLV1544CPWR",
        "status": "found"
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    },
    "pins": [
      {
        "number": "1",
        "name": "DATA OUT",
        "type": "tri_state",
        "description": "Three-state serial output of the A/D conversion result, in high-impedance when CS is high and active when CS is low (or after FS↓ in DSP mode), changing on the falling (microprocessor mode) or rising (DSP mode) edge of I/O CLK."
      },
      {
        "number": "2",
        "name": "DATA IN",
        "type": "input",
        "description": "Serial data input that receives the 4-bit MSB-first channel and mode select word on the first four I/O CLK edges, and is ignored for the rest of the current conversion period."
      },
      {
        "number": "3",
        "name": "I/O CLK",
        "type": "input",
        "description": "Input/output clock that clocks in the input data bits, sets sampling and conversion timing, and shifts out output data; the datasheet states it can go up to 10 MHz for most of the voltage range and is limited to 2.8 MHz for a supply from 2.7 V."
      },
      {
        "number": "4",
        "name": "EOC",
        "type": "output",
        "description": "End-of-conversion output that goes low on the tenth rising (microprocessor mode) or tenth falling (DSP mode) I/O CLK edge and stays low until the conversion is complete and data is ready for transfer."
      },
      {
        "number": "5",
        "name": "VCC",
        "type": "power_in",
        "description": "Positive supply voltage; the device is specified for single-supply operation from 2.7 V dc to 5.5 V dc."
      },
      {
        "number": "6",
        "name": "A0",
        "type": "input",
        "description": "Analog input channel 0, internally multiplexed; for a source impedance greater than 1 kΩ, the asynchronous start should be used to increase the sampling time."
      },
      {
        "number": "7",
        "name": "A1",
        "type": "input",
        "description": "Analog input channel 1, internally multiplexed; for a source impedance greater than 1 kΩ, the asynchronous start should be used to increase the sampling time."
      },
      {
        "number": "8",
        "name": "A2",
        "type": "input",
        "description": "Analog input channel 2, internally multiplexed; for a source impedance greater than 1 kΩ, the asynchronous start should be used to increase the sampling time."
      },
      {
        "number": "9",
        "name": "A3",
        "type": "input",
        "description": "Analog input channel 3, internally multiplexed; for a source impedance greater than 1 kΩ, the asynchronous start should be used to increase the sampling time."
      },
      {
        "number": "10",
        "name": "CSTART",
        "type": "input",
        "description": "Sampling/conversion start control where a high-to-low transition starts sampling and a low-to-high transition starts conversion, independent of I/O CLK and working while CS is high; it must be tied to VCC if not used."
      },
      {
        "number": "11",
        "name": "GND",
        "type": "power_in",
        "description": "Ground return for internal circuitry; all voltage measurements are referenced to GND unless otherwise noted."
      },
      {
        "number": "12",
        "name": "INV CLK",
        "type": "input",
        "description": "Inverted clock input that is tied to GND when an inverted I/O CLK is used and to VCC when it is not, affecting both microprocessor and DSP interfaces, and can also invoke a built-in test mode."
      },
      {
        "number": "13",
        "name": "FS",
        "type": "input",
        "description": "DSP frame synchronization input that indicates the start of a serial data frame into or out of the device, and is tied to VCC when interfacing with a microprocessor."
      },
      {
        "number": "14",
        "name": "REF–",
        "type": "input",
        "description": "Lower reference voltage, nominally ground, that together with REF+ sets the maximum input voltage range."
      },
      {
        "number": "15",
        "name": "REF+",
        "type": "input",
        "description": "Upper reference voltage, nominally VCC; the maximum input voltage range is determined by the difference between the voltages applied to REF+ and REF-."
      },
      {
        "number": "16",
        "name": "CS",
        "type": "input",
        "description": "Chip select where a high-to-low transition resets the internal counters and enables DATA IN, DATA OUT and I/O CLK within the maximum setup time, and a low-to-high transition disables them within the setup time."
      }
    ],
    "provenance": {
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        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Pin numbers are the D/PW numbering. The Terminal Functions table footnote labels its first number co; The TLV1544 has only four analog inputs (A0–A3). A4–A7 belong to the TLV1548 and are not part of the; The datasheet's orderable list (page 32) shows TLV1544CPWR as a 16-pin TSSOP (PW) package, which con"
        ],
        "pages_sent": 9,
        "cost_usd": 0.0703,
        "at": "2026-10-11T09:02:49"
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        "url": "https://www.ti.com/cn/lit/gpn/tlv1544",
        "pages": 38,
        "sha256": "6a6c65b5e7263803",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
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}