component

TLP7830

Public Made by Adom

by adom

TOSHIBA Pre-Ordered Products, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentelectronic tools-instruments-consumablestlp7830factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 5d ago
viewers tlp7830: viewers · Ray 5d ago
package.json Publish 0.1.0 · Ray 5d ago
page.json Set visibility: public · Ray 5d ago
README.md Publish 0.1.0 · Ray 5d ago
tlp7830-etched.glb Publish 0.1.0 · Ray 5d ago
tlp7830-etched.step tlp7830: factory component page (tier=lcsc) · Ray 5d ago
tlp7830-hero.glb tlp7830: hero GLB from the etched model (keeps the MPN mark) · Ray 5d ago
tlp7830-hero.overlay.json Publish 0.1.0 · Ray 5d ago
tlp7830.glb Publish 0.1.0 · Ray 5d ago
tlp7830.kicad_mod Publish 0.1.0 · Ray 5d ago
tlp7830.kicad_sym Publish 0.1.0 · Ray 5d ago
tlp7830.lbr Publish 0.1.0 · Ray 5d ago
tlp7830.step Publish 0.1.0 · Ray 5d ago

TLP7830

TOSHIBA · Pre-Ordered Products · SO-8

TLP7830 from TOSHIBA, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Input side supply voltage, recommended 4.5 to 5.5 V, requiring a 0.1 µF bypass capacitor to pin 4.
2 VIN+ power_in Positive analog input, specified for -200 to 200 mV (FSR ±320 mV), and must not be raised to VDD1 - 2 V or above to stay in functional mode.
3 VIN- power_in Negative analog input, specified for -200 to 200 mV, and must not be raised to VDD1 - 2 V or above to stay in functional mode.
4 GND1 power_in Input side ground, serving as the return for VDD1 and requiring a 0.1 µF bypass capacitor to pin 1.
5 GND2 power_in Output side ground, requiring a 0.1 µF bypass capacitor to pin 8.
6 MDAT output Modulator data output, with the digital output voltage rated -0.5 to 6 V (absolute maximum) and output power dissipation of 48 mW.
7 MCLK output Modulator clock output, running at 10 MHz typical (8.5 to 11.5 MHz) with a 15 pF load.
8 VDD2 power_in Output side supply voltage, specified for 3 to 5.5 V.

Key specifications

Parameter Value
Manufacturer TOSHIBA
Package SO-8
Category Electronic Tools/Instruments/Consumables
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input side supply voltage (VDD1) VDD1 4.5 5 5.5 V 3
Output side supply voltage (VDD2) VDD2 3 5.5 V 3
Analog input voltage VIN+, VIN- -200 200 mV FSR = ±320 mV 3
Ambient temperature Ta -40 105 °C 3
Supply voltages VDD1, VDD2 -0.5 6 V 3
Steady-state input voltages (lower limit; upper limit VDD1 + 0.5 V) VIN+, VIN- -0.5 V 3
Two-second transient input voltages (lower limit; upper limit VDD1 + 0.5 V) VIN+, VIN- -6 V 3
Input power dissipation PD 72 mW 3
Input power dissipation derating ∆PD/∆Ta -5 mW/°C Ta ≥ 110.6 °C 3
Digital output voltage MCLK, MDAT -0.5 6 V 3
Output power dissipation PO 48 mW 3
Output power dissipation derating ∆PO/∆Ta -5 mW/°C Ta ≥ 115.4 °C 3
Operating temperature Topr -40 105 °C 3
Storage temperature Tstg -55 125 °C 3
Lead soldering temperature Tsol 260 °C 10 s 3
Isolation voltage BVS 5000 Vrms AC, 60 s, R.H. ≤ 60 % 5
Output clock frequency fCLK 8.5 10 11.5 MHz CL = 15 pF 5
Access time after MCLK rising edge tath 33 45 ns CL = 15 pF 5
Hold time after MCLK rising edge tath 10 24 ns CL = 15 pF 5
Common-mode transient immunity CMTI 15 20 kV/µs VCM = 1 kV, Ta = 25 °C 5
Integral non-linearity INL -15 15 LSB Ta = -40 to 85 °C 4
Integral non-linearity INL -25 25 LSB Ta = 105 °C 4
Input offset voltage VOS -0.9 0.6 0.9 mV Ta = 25 °C 4
High-level output voltage VOH 3.1 3.2 V IOUT = -200 µA, VDD2 = 3.3 V 4
High-level output voltage VOH 4.8 4.9 V IOUT = -200 µA, VDD2 = 5 V 4
Low-level output voltage VOL 0.03 0.05 V IOUT = 200 µA 4
Input common-mode rejection ratio CMRRIN 68 74 dB 4

CAD (KiCad official)

  • Symbol: TLP7830
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)
  • 3D model files: tlp7830-etched.step / tlp7830-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlp7830.step / tlp7830.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TOSHIBA datasheet (15 pp, sha256 046c03003c4fcbfa, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF