TLC1550IDWR

{
  "slug": "tlc1550idwr",
  "version": "0.1.0",
  "type": "component",
  "description": "Texas Instruments Analog To Digital Converters (ADCs), SOIC-24-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "adc-dac-data conversion",
    "tlc1550idwr",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "tlc1550idwr.kicad_sym",
    "tlc1550idwr.kicad_mod",
    "tlc1550idwr.glb",
    "tlc1550idwr.step",
    "tlc1550idwr.lbr",
    "docs/hero.png",
    "docs/tlc1550idwr-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "tlc1550idwr-hero.glb",
    "tlc1550idwr-hero.overlay.json",
    "tlc1550idwr-etched.glb"
  ],
  "component": {
    "mpn": "TLC1550IDWR",
    "manufacturer": "Texas Instruments",
    "package": "SOIC-24-300mil",
    "pin_count": 24,
    "category": "ADC/DAC/Data Conversion",
    "subcategory": "Analog To Digital Converters (ADCs)",
    "datasheet": "https://www.ti.com/lit/ds/symlink/tlc1550idwr.pdf",
    "parts": {
      "symbol": "tlc1550idwr.kicad_sym",
      "footprint": "tlc1550idwr.kicad_mod",
      "model_3d": "tlc1550idwr-hero.glb",
      "model_3d_plain": "tlc1550idwr-etched.glb",
      "model_3d_step": "tlc1550idwr-etched.step",
      "model_3d_step_plain": "tlc1550idwr.step",
      "lbr": "tlc1550idwr.lbr"
    },
    "distributor_links": {
      "lcsc": "C2866355",
      "digikey": "TLC1550IDWR-ND",
      "mouser": "595-TLC1550IDWR"
    },
    "distributor_check": {
      "checked_at": "2026-11-02T19:22:56Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "TLC1550IDWR-ND",
        "status": "found",
        "lifecycle": "Active"
      },
      "mouser": {
        "pn": "595-TLC1550IDWR",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "REF+",
        "type": "input",
        "description": "Positive voltage-reference input; analog inputs greater than or equal to REF+ convert to 1111111111."
      },
      {
        "number": "2",
        "name": "REF−",
        "type": "input",
        "description": "Negative voltage-reference input; analog inputs less than or equal to REF− convert to 0000000000."
      },
      {
        "number": "3",
        "name": "ANLG GND",
        "type": "power_in",
        "description": "Analog ground, the reference point for the voltage applied on ANLG VDD, AIN, REF+, and REF−."
      },
      {
        "number": "4",
        "name": "AIN",
        "type": "input",
        "description": "Analog voltage input whose applied voltage is converted to the equivalent digital output."
      },
      {
        "number": "5",
        "name": "ANLG VDD",
        "type": "power_in",
        "description": "Analog positive power supply voltage (VDD3), recommended 4.75 V to 5.5 V."
      },
      {
        "number": "6",
        "name": "DGTL GND1",
        "type": "power_in",
        "description": "Digital ground 1, the ground for DGTL VDD1 and the substrate connection."
      },
      {
        "number": "7",
        "name": "DGTL GND2",
        "type": "power_in",
        "description": "Digital ground 2, the ground for power supply DGTL VDD2."
      },
      {
        "number": "8",
        "name": "DGTL VDD1",
        "type": "power_in",
        "description": "Digital positive power supply 1 (VDD1) that supplies the logic, recommended 4.75 V to 5.5 V."
      },
      {
        "number": "9",
        "name": "DGTL VDD2",
        "type": "power_in",
        "description": "Digital positive power supply 2 (VDD2) that supplies only the higher-current output buffers, recommended 4.75 V to 5.5 V."
      },
      {
        "number": "10",
        "name": "EOC",
        "type": "output",
        "description": "End-of-conversion output that goes low when conversion is complete and results are in the output latch, and is reset high by the falling edge of RD."
      },
      {
        "number": "11",
        "name": "D0",
        "type": "tri_state",
        "description": "Data bus output D0, bit 1 (LSB)."
      },
      {
        "number": "12",
        "name": "D1",
        "type": "tri_state",
        "description": "Data bus output D1, bit 2."
      },
      {
        "number": "13",
        "name": "D2",
        "type": "tri_state",
        "description": "Data bus output D2, bit 3."
      },
      {
        "number": "14",
        "name": "D3",
        "type": "tri_state",
        "description": "Data bus output D3, bit 4."
      },
      {
        "number": "15",
        "name": "D4",
        "type": "tri_state",
        "description": "Data bus output D4, bit 5."
      },
      {
        "number": "16",
        "name": "D5",
        "type": "tri_state",
        "description": "Data bus output D5, bit 6."
      },
      {
        "number": "17",
        "name": "D6",
        "type": "tri_state",
        "description": "Data bus output D6, bit 7."
      },
      {
        "number": "18",
        "name": "D7",
        "type": "tri_state",
        "description": "Data bus output D7, bit 8."
      },
      {
        "number": "19",
        "name": "D8",
        "type": "tri_state",
        "description": "Data bus output D8, bit 9."
      },
      {
        "number": "20",
        "name": "D9",
        "type": "tri_state",
        "description": "Data bus output D9, bit 10 (MSB)."
      },
      {
        "number": "21",
        "name": "CS",
        "type": "input",
        "description": "Chip-select input that must be low for RD or WR to be recognized by the converter."
      },
      {
        "number": "22",
        "name": "CLKIN",
        "type": "input",
        "description": "External clock input (0.5 MHz to 7.8 MHz) that overrides the internal clock; tie high or leave unconnected to use the internal clock."
      },
      {
        "number": "23",
        "name": "WR",
        "type": "input",
        "description": "Write input; when CS is low, conversion starts on the rising edge of WR and the ADC holds the analog input until conversion completes."
      },
      {
        "number": "24",
        "name": "RD",
        "type": "input",
        "description": "Read input; when CS and RD are low the output latch data is placed on the data bus, and the falling edge of RD resets EOC high."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-sonnet-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-opus-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [],
        "pages_sent": 20,
        "cost_usd": 0.2229,
        "at": "2026-11-02T19:22:20"
      },
      "datasheet": {
        "url": "https://www.ti.com/lit/ds/symlink/tlc1550idwr.pdf",
        "pages": 20,
        "sha256": "5cd6b461f7ba6239",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 24,
        "described": 24,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "tlc1550idwr.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          10.3,
          15.4,
          2.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "4b0d20f82f5b0124fecfe11c941274a3c865a30f7baee8b8fadd7df55972d4cd",
        "checked": "2026-11-02",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "tlc1550idwr-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          10.3,
          15.4,
          2.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "290014918f9fef1f4b8b57d49b1eeb167097c9f90ae1c14b35becc99daaba93d",
        "checked": "2026-11-02",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ],
    "package_dims": {
      "package_code": "DW",
      "E1": {
        "nom_mm": 7.5,
        "range_mm": null
      },
      "E": {
        "nom_mm": 10.3,
        "range_mm": null
      },
      "e": {
        "nom_mm": 1.27,
        "range_mm": null
      },
      "source": "TI package designator DW (no drawing in the datasheet)",
      "model_check": {
        "file": "tlc1550idwr.step",
        "verdict": "SKIP",
        "reasons": [
          "the datasheet dimensions give no height or body size to compare"
        ],
        "by": "factory/package_fit.py"
      }
    }
  }
}