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TLC1550IDWR

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Texas Instruments Analog To Digital Converters (ADCs), SOIC-24-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentadc-dac-data conversiontlc1550idwrfactory-2.0.0extractor-text

Verified TLC1550IDWR

by Ray · last 2 Nov 2026 · 1 record · files match
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Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 24 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: TLC1550IDWR · SOIC-24-300mil · 24 pins
  • ✓copper: 24 copper pads, none touching another net
  • ✓datasheet: all 24 pin names found in the 20-page datasheet
  • ✓distributor: lcsc C2866355, digikey TLC1550IDWR-ND, mouser 595-TLC1550IDWR
  • ✓family: SOIC-24W_7.5x15.4mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-lljt1pqk/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): the datasheet dimensions give no height or body size to compare
  • ✓pads: 24 pins = 24 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 24 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ tlc1550idwr.kicad_sym✓ tlc1550idwr.kicad_mod✓ tlc1550idwr.step
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Contents

README

markdown

TLC1550IDWR

Texas Instruments · Analog To Digital Converters (ADCs) · SOIC-24-300mil

TLC1550IDWR from Texas Instruments, in a SOIC-24-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 REF+ input Positive voltage-reference input; analog inputs greater than or equal to REF+ convert to 1111111111.
2 REF− input Negative voltage-reference input; analog inputs less than or equal to REF− convert to 0000000000.
3 ANLG GND power_in Analog ground, the reference point for the voltage applied on ANLG VDD, AIN, REF+, and REF−.
4 AIN input Analog voltage input whose applied voltage is converted to the equivalent digital output.
5 ANLG VDD power_in Analog positive power supply voltage (VDD3), recommended 4.75 V to 5.5 V.
6 DGTL GND1 power_in Digital ground 1, the ground for DGTL VDD1 and the substrate connection.
7 DGTL GND2 power_in Digital ground 2, the ground for power supply DGTL VDD2.
8 DGTL VDD1 power_in Digital positive power supply 1 (VDD1) that supplies the logic, recommended 4.75 V to 5.5 V.
9 DGTL VDD2 power_in Digital positive power supply 2 (VDD2) that supplies only the higher-current output buffers, recommended 4.75 V to 5.5 V.
10 EOC output End-of-conversion output that goes low when conversion is complete and results are in the output latch, and is reset high by the falling edge of RD.
11 D0 tri_state Data bus output D0, bit 1 (LSB).
12 D1 tri_state Data bus output D1, bit 2.
13 D2 tri_state Data bus output D2, bit 3.
14 D3 tri_state Data bus output D3, bit 4.
15 D4 tri_state Data bus output D4, bit 5.
16 D5 tri_state Data bus output D5, bit 6.
17 D6 tri_state Data bus output D6, bit 7.
18 D7 tri_state Data bus output D7, bit 8.
19 D8 tri_state Data bus output D8, bit 9.
20 D9 tri_state Data bus output D9, bit 10 (MSB).
21 CS input Chip-select input that must be low for RD or WR to be recognized by the converter.
22 CLKIN input External clock input (0.5 MHz to 7.8 MHz) that overrides the internal clock; tie high or leave unconnected to use the internal clock.
23 WR input Write input; when CS is low, conversion starts on the rising edge of WR and the ADC holds the analog input until conversion completes.
24 RD input Read input; when CS and RD are low the output latch data is placed on the data bus, and the falling edge of RD resets EOC high.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-24-300mil
Category ADC/DAC/Data Conversion
Pins 24

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD1, VDD2, VDD3 6.5 V see Note 1 4
Input voltage range (any input) VI -0.3 V -0.3 V to VDD + 0.3 V 4
Output voltage range VO -0.3 V -0.3 V to VDD + 0.3 V 4
Peak input current (any digital input) -10 10 mA 4
Peak total input current (all inputs) -30 30 mA 4
Operating free-air temperature range TA -40 85 °C TLC1550I 4
Storage temperature range Tstg -65 150 °C 4
Supply voltage VDD1, VDD2, VDD3 4.75 5 5.5 V 4
Negative reference voltage VREF− 0 V see Note 2 4
Analog input voltage range 0 V 0 to VDD3 4
High-level control input voltage VIH 2 V 4
Low-level control input voltage VIL 0.8 V 4
Input clock frequency f(CLKIN) 0.5 7.8 MHz 4
Setup time, CS low before WR or RD low tsu(CS) 0 ns 4
Hold time, CS low after WR or RD high th(CS) 0 ns 4
WR or RD pulse duration tw(WR) 50 ns 4
Operating free-air temperature TA -40 85 °C TLC155xI 4
High-level output voltage VOH 2.4 V VDD = 4.75 V, IOH = −360 µA 5
Low-level output voltage VOL 0.4 V VDD = 4.75 V, IOL = 2.4 mA, TA = 25°C 5
Off-state output current IOZ 10 µA VO = VDD, CS and RD at VDD 5
Off-state output current IOZ -10 µA VO = 0, CS and RD at VDD 5
High-level input current IIH 0.005 2.5 µA VI = VDD 5
Low-level input current (except CLKIN) IIL -2.5 -0.005 µA VI = 0 5
Low-level input current (CLKIN) IIL -50 -50 µA 5
Short-circuit output current IOS 7 14 mA VO = 5 V, TA = 25°C 5
Short-circuit output current IOS -12 -6 mA VO = 0, TA = 25°C 5
Operating supply current I(DD) 2 8 mA CS low and RD high 5
Input capacitance, analog inputs Ci 60 90 pF See typical equivalent inputs, TLC1550/1I 5
Input capacitance, digital inputs Ci 5 15 pF See typical equivalent inputs, TLC1550/1I 5
Linearity error EL -0.5 0.5 LSB TLC1550I, Full range, See Note 3 6
Zero-scale error EZS -0.5 0.5 LSB TLC1550I, Full range, See Notes 2 and 4 6
Full-scale error EFS -0.5 0.5 LSB TLC1550I, Full range, See Notes 2 and 4 6
Total unadjusted error -0.5 0.5 LSB TLC1550I, Full range, See Note 5 6
Conversion time tc 6 µs fclock(external) = 4.2 MHz or internal clock 6
Data access time after RD goes low ta(D) 35 ns 6
Data valid time after RD goes high tv(D) 5 ns 6
Disable time, RD high to high impedance tdis(D) 30 ns See Figure 3 6
Delay time, RD low to EOC high td(EOC) 0 15 ns 6

CAD (KiCad official)

  • Symbol: TLC1550IDWR
  • Footprint: Package_SO:SOIC-24W_7.5x15.4mm_P1.27mm
  • 3D model: SOIC-24-300mil (KiCad packages3D, STEP)
  • 3D model files: tlc1550idwr-etched.step / tlc1550idwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlc1550idwr.step / tlc1550idwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (20 pp, sha256 5cd6b461f7ba6239, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF