TL16C550DPTR

{
  "schema_version": 1,
  "type": "component",
  "slug": "tl16c550dptr",
  "title": "TL16C550DPTR",
  "brief": "Texas Instruments UART, LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
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    "interface",
    "tl16c550dptr",
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    "extractor-text"
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  "component": {
    "mpn": "TL16C550DPTR",
    "manufacturer": "Texas Instruments",
    "package": "LQFP-48(7x7)",
    "pin_count": 48,
    "category": "Interface",
    "subcategory": "UART",
    "datasheet": "https://www.ti.com/cn/lit/gpn/tl16c550d",
    "parts": {
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      "footprint": "tl16c550dptr.kicad_mod",
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      "model_3d_plain": "tl16c550dptr.glb",
      "model_3d_step": "tl16c550dptr-etched.step",
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      "lbr": "tl16c550dptr.lbr"
    },
    "distributor_links": {
      "lcsc": "C544406",
      "digikey": "296-TL16C550DPTR-ND",
      "mouser": "595-TL16C550DPTR"
    },
    "distributor_check": {
      "checked_at": "2026-10-07T23:43:20Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "296-TL16C550DPTR-ND",
        "status": "found",
        "lifecycle": "Active"
      },
      "mouser": {
        "pn": "595-TL16C550DPTR",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "NC",
        "type": "unconnected",
        "description": "No internal connection; leave this pin unconnected."
      },
      {
        "number": "2",
        "name": "D5",
        "type": "bidirectional",
        "description": "Data bus line D5 provides a bidirectional 3-state path for data, control and status between the ACE and the CPU."
      },
      {
        "number": "3",
        "name": "D6",
        "type": "bidirectional",
        "description": "Data bus line D6 provides a bidirectional 3-state path for data, control and status between the ACE and the CPU."
      },
      {
        "number": "4",
        "name": "D7",
        "type": "bidirectional",
        "description": "Data bus line D7 provides a bidirectional 3-state path for data, control and status between the ACE and the CPU."
      },
      {
        "number": "5",
        "name": "RCLK",
        "type": "input",
        "description": "Receiver clock is the 16x baud rate clock for the receiver section of the ACE."
      },
      {
        "number": "6",
        "name": "NC",
        "type": "unconnected",
        "description": "No internal connection; leave this pin unconnected."
      },
      {
        "number": "7",
        "name": "SIN",
        "type": "input",
        "description": "Serial data input receives serial data from the connected communications device."
      },
      {
        "number": "8",
        "name": "SOUT",
        "type": "output",
        "description": "Serial data output sends composite serial data to the connected communication device and is set to marking (high) by master reset."
      },
      {
        "number": "9",
        "name": "CS0",
        "type": "input",
        "description": "Chip select 0: with CS1 high and CS2 low, these inputs select the ACE; when any chip select is inactive the ACE remains inactive."
      },
      {
        "number": "10",
        "name": "CS1",
        "type": "input",
        "description": "Chip select 1: with CS0 high and CS2 low, these inputs select the ACE; when any chip select is inactive the ACE remains inactive."
      },
      {
        "number": "11",
        "name": "CS2",
        "type": "input",
        "description": "Chip select 2: with CS0 and CS1 high and CS2 low, this input selects the ACE; when inactive the ACE remains inactive."
      },
      {
        "number": "12",
        "name": "BAUDOUT",
        "type": "output",
        "description": "Baud out provides a 16x transmitter clock whose rate is set by the reference oscillator divided by the baud generator divisor; it may be tied to RCLK for receiver clocking."
      },
      {
        "number": "13",
        "name": "NC",
        "type": "unconnected",
        "description": "No internal connection; leave this pin unconnected."
      },
      {
        "number": "14",
        "name": "XIN",
        "type": "bidirectional",
        "description": "External clock input connects the ACE to the main timing reference (clock or crystal) together with XOUT."
      },
      {
        "number": "15",
        "name": "XOUT",
        "type": "bidirectional",
        "description": "External clock output connects the ACE to the main timing reference (crystal) together with XIN."
      },
      {
        "number": "16",
        "name": "WR1",
        "type": "input",
        "description": "Write input 1: when active (low) with WR2 tied inactive (high) and the ACE selected, the CPU may write control words or data."
      },
      {
        "number": "17",
        "name": "WR2",
        "type": "input",
        "description": "Write input 2: when active (high) with WR1 tied inactive (low) and the ACE selected, the CPU may write control words or data."
      },
      {
        "number": "18",
        "name": "VSS",
        "type": "power_in",
        "description": "Supply common (ground) for the device."
      },
      {
        "number": "19",
        "name": "RD1",
        "type": "input",
        "description": "Read input 1: when active (low) with the ACE selected, the CPU may read status or data from the selected ACE register; RD2 must be tied to its inactive level."
      },
      {
        "number": "20",
        "name": "RD2",
        "type": "input",
        "description": "Read input 2: when active (high) with the ACE selected, the CPU may read status or data from the selected ACE register; RD1 must be tied to its inactive level."
      },
      {
        "number": "21",
        "name": "NC",
        "type": "unconnected",
        "description": "No internal connection; leave this pin unconnected."
      },
      {
        "number": "22",
        "name": "DDIS",
        "type": "output",
        "description": "Driver disable is active (high) when the CPU is not reading data and can disable an external transceiver."
      },
      {
        "number": "23",
        "name": "TXRDY",
        "type": "output",
        "description": "Transmitter ready provides transmitter DMA signaling (mode 0 single transfer or mode 1 multitransfer, selected by FCR3 in FIFO mode)."
      },
      {
        "number": "24",
        "name": "ADS",
        "type": "input",
        "description": "Address strobe: when active (low), A0-A2 and CS0-CS2 drive the select logic directly; when high, they are held at their levels at the low-to-high ADS transition."
      },
      {
        "number": "25",
        "name": "NC",
        "type": "unconnected",
        "description": "No internal connection; leave this pin unconnected."
      },
      {
        "number": "26",
        "name": "A2",
        "type": "input",
        "description": "Register select bit 2 selects the ACE register for read or write operations (see Table 1)."
      },
      {
        "number": "27",
        "name": "A1",
        "type": "input",
        "description": "Register select bit 1 selects the ACE register for read or write operations (see Table 1)."
      },
      {
        "number": "28",
        "name": "A0",
        "type": "input",
        "description": "Register select bit 0 selects the ACE register for read or write operations (see Table 1)."
      },
      {
        "number": "29",
        "name": "RXRDY",
        "type": "output",
        "description": "Receiver ready provides receiver DMA signaling (mode 0 single transfer or mode 1 multitransfer, selected by FCR3 in FIFO mode) and goes active low when data is available."
      },
      {
        "number": "30",
        "name": "INTRPT",
        "type": "output",
        "description": "Interrupt output is active (high) to inform the CPU of a receiver error, received data, an empty transmitter holding register or a modem status interrupt."
      },
      {
        "number": "31",
        "name": "OUT2",
        "type": "output",
        "description": "User-designated output 2 is forced low when MCR bit 3 is set and high when cleared, and is high after master reset."
      },
      {
        "number": "32",
        "name": "RTS",
        "type": "output",
        "description": "Request to send is active (low) when set by the RTS MCR bit, inactive (high) after master reset, and is controlled by receiver threshold logic in auto-RTS mode."
      },
      {
        "number": "33",
        "name": "DTR",
        "type": "output",
        "description": "Data terminal ready is active (low) when the DTR MCR bit is set and inactive after master reset, loop mode, or clearing the DTR bit."
      },
      {
        "number": "34",
        "name": "OUT1",
        "type": "output",
        "description": "User-designated output 1 is forced low when MCR bit 2 is set and high when cleared, and is high after master reset."
      },
      {
        "number": "35",
        "name": "MR",
        "type": "input",
        "description": "Master reset: when active (high) it clears most ACE registers and sets the levels of various output signals."
      },
      {
        "number": "36",
        "name": "NC",
        "type": "unconnected",
        "description": "No internal connection; leave this pin unconnected."
      },
      {
        "number": "37",
        "name": "NC",
        "type": "unconnected",
        "description": "No internal connection; leave this pin unconnected."
      },
      {
        "number": "38",
        "name": "CTS",
        "type": "input",
        "description": "Clear to send is a modem status input that also controls the transmitter in auto-CTS mode."
      },
      {
        "number": "39",
        "name": "DSR",
        "type": "input",
        "description": "Data set ready is a modem status input whose condition is read from MSR bit 5 and which generates an interrupt on change when enabled."
      },
      {
        "number": "40",
        "name": "DCD",
        "type": "input",
        "description": "Data carrier detect is a modem status input whose condition is read from MSR bit 7 and which generates an interrupt on change when enabled."
      },
      {
        "number": "41",
        "name": "RI",
        "type": "input",
        "description": "Ring indicator is a modem status input whose condition is read from MSR bit 6 and which generates an interrupt on a low-to-high transition when enabled."
      },
      {
        "number": "42",
        "name": "VCC",
        "type": "power_in",
        "description": "Power supply input, 2.25 V to 5.5 V."
      },
      {
        "number": "43",
        "name": "D0",
        "type": "bidirectional",
        "description": "Data bus line D0 provides a bidirectional 3-state path for data, control and status between the ACE and the CPU."
      },
      {
        "number": "44",
        "name": "D1",
        "type": "bidirectional",
        "description": "Data bus line D1 provides a bidirectional 3-state path for data, control and status between the ACE and the CPU."
      },
      {
        "number": "45",
        "name": "D2",
        "type": "bidirectional",
        "description": "Data bus line D2 provides a bidirectional 3-state path for data, control and status between the ACE and the CPU."
      },
      {
        "number": "46",
        "name": "D3",
        "type": "bidirectional",
        "description": "Data bus line D3 provides a bidirectional 3-state path for data, control and status between the ACE and the CPU."
      },
      {
        "number": "47",
        "name": "D4",
        "type": "bidirectional",
        "description": "Data bus line D4 provides a bidirectional 3-state path for data, control and status between the ACE and the CPU."
      },
      {
        "number": "48",
        "name": "NC",
        "type": "unconnected",
        "description": "No internal connection; leave this pin unconnected."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Package match: the ordering table (pages 43-44) lists TL16C550DPTR as LQFP (PT), 48 pins, 0 to 70 °C; XIN and XOUT are labeled I/O in the datasheet, so they are typed bidirectional as printed. Verify th; Pins 1, 6, 13, 21, 25, 36, 37 and 48 are all printed as NC in the datasheet and are listed individua"
        ],
        "pages_sent": 18,
        "cost_usd": 0.1435,
        "at": "2026-10-07T23:42:57"
      },
      "datasheet": {
        "url": "https://www.ti.com/cn/lit/gpn/tl16c550d",
        "pages": 60,
        "sha256": "a49ab32dac5b1c13",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 48,
        "described": 48,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
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        "checked": "2026-10-07",
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      },
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        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "Texas Instruments",
      "Package": "LQFP-48(7x7)",
      "Category": "Interface",
      "Pins": "48"
    }
  },
  "variants": [],
  "sections": [
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  "discovery_triggers": [
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  "discovery_pitch": "TL16C550DPTR (Texas Instruments) component page: datasheet pinout, KiCad symbol, footprint and 3D.",
  "author": {
    "name": "Ray",
    "email": "[email protected]"
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