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TL16C550DPTR

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Texas Instruments UART, LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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TL16C550DPTR

Texas Instruments · UART · LQFP-48(7x7)

TL16C550DPTR from Texas Instruments, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No internal connection; leave this pin unconnected.
2 D5 bidirectional Data bus line D5 provides a bidirectional 3-state path for data, control and status between the ACE and the CPU.
3 D6 bidirectional Data bus line D6 provides a bidirectional 3-state path for data, control and status between the ACE and the CPU.
4 D7 bidirectional Data bus line D7 provides a bidirectional 3-state path for data, control and status between the ACE and the CPU.
5 RCLK input Receiver clock is the 16x baud rate clock for the receiver section of the ACE.
6 NC unconnected No internal connection; leave this pin unconnected.
7 SIN input Serial data input receives serial data from the connected communications device.
8 SOUT output Serial data output sends composite serial data to the connected communication device and is set to marking (high) by master reset.
9 CS0 input Chip select 0: with CS1 high and CS2 low, these inputs select the ACE; when any chip select is inactive the ACE remains inactive.
10 CS1 input Chip select 1: with CS0 high and CS2 low, these inputs select the ACE; when any chip select is inactive the ACE remains inactive.
11 CS2 input Chip select 2: with CS0 and CS1 high and CS2 low, this input selects the ACE; when inactive the ACE remains inactive.
12 BAUDOUT output Baud out provides a 16x transmitter clock whose rate is set by the reference oscillator divided by the baud generator divisor; it may be tied to RCLK for receiver clocking.
13 NC unconnected No internal connection; leave this pin unconnected.
14 XIN bidirectional External clock input connects the ACE to the main timing reference (clock or crystal) together with XOUT.
15 XOUT bidirectional External clock output connects the ACE to the main timing reference (crystal) together with XIN.
16 WR1 input Write input 1: when active (low) with WR2 tied inactive (high) and the ACE selected, the CPU may write control words or data.
17 WR2 input Write input 2: when active (high) with WR1 tied inactive (low) and the ACE selected, the CPU may write control words or data.
18 VSS power_in Supply common (ground) for the device.
19 RD1 input Read input 1: when active (low) with the ACE selected, the CPU may read status or data from the selected ACE register; RD2 must be tied to its inactive level.
20 RD2 input Read input 2: when active (high) with the ACE selected, the CPU may read status or data from the selected ACE register; RD1 must be tied to its inactive level.
21 NC unconnected No internal connection; leave this pin unconnected.
22 DDIS output Driver disable is active (high) when the CPU is not reading data and can disable an external transceiver.
23 TXRDY output Transmitter ready provides transmitter DMA signaling (mode 0 single transfer or mode 1 multitransfer, selected by FCR3 in FIFO mode).
24 ADS input Address strobe: when active (low), A0-A2 and CS0-CS2 drive the select logic directly; when high, they are held at their levels at the low-to-high ADS transition.
25 NC unconnected No internal connection; leave this pin unconnected.
26 A2 input Register select bit 2 selects the ACE register for read or write operations (see Table 1).
27 A1 input Register select bit 1 selects the ACE register for read or write operations (see Table 1).
28 A0 input Register select bit 0 selects the ACE register for read or write operations (see Table 1).
29 RXRDY output Receiver ready provides receiver DMA signaling (mode 0 single transfer or mode 1 multitransfer, selected by FCR3 in FIFO mode) and goes active low when data is available.
30 INTRPT output Interrupt output is active (high) to inform the CPU of a receiver error, received data, an empty transmitter holding register or a modem status interrupt.
31 OUT2 output User-designated output 2 is forced low when MCR bit 3 is set and high when cleared, and is high after master reset.
32 RTS output Request to send is active (low) when set by the RTS MCR bit, inactive (high) after master reset, and is controlled by receiver threshold logic in auto-RTS mode.
33 DTR output Data terminal ready is active (low) when the DTR MCR bit is set and inactive after master reset, loop mode, or clearing the DTR bit.
34 OUT1 output User-designated output 1 is forced low when MCR bit 2 is set and high when cleared, and is high after master reset.
35 MR input Master reset: when active (high) it clears most ACE registers and sets the levels of various output signals.
36 NC unconnected No internal connection; leave this pin unconnected.
37 NC unconnected No internal connection; leave this pin unconnected.
38 CTS input Clear to send is a modem status input that also controls the transmitter in auto-CTS mode.
39 DSR input Data set ready is a modem status input whose condition is read from MSR bit 5 and which generates an interrupt on change when enabled.
40 DCD input Data carrier detect is a modem status input whose condition is read from MSR bit 7 and which generates an interrupt on change when enabled.
41 RI input Ring indicator is a modem status input whose condition is read from MSR bit 6 and which generates an interrupt on a low-to-high transition when enabled.
42 VCC power_in Power supply input, 2.25 V to 5.5 V.
43 D0 bidirectional Data bus line D0 provides a bidirectional 3-state path for data, control and status between the ACE and the CPU.
44 D1 bidirectional Data bus line D1 provides a bidirectional 3-state path for data, control and status between the ACE and the CPU.
45 D2 bidirectional Data bus line D2 provides a bidirectional 3-state path for data, control and status between the ACE and the CPU.
46 D3 bidirectional Data bus line D3 provides a bidirectional 3-state path for data, control and status between the ACE and the CPU.
47 D4 bidirectional Data bus line D4 provides a bidirectional 3-state path for data, control and status between the ACE and the CPU.
48 NC unconnected No internal connection; leave this pin unconnected.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-48(7x7)
Category Interface
Pins 48

CAD (KiCad official)

  • Symbol: TL16C550DPTR
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: tl16c550dptr-etched.step / tl16c550dptr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tl16c550dptr.step / tl16c550dptr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (60 pp, sha256 a49ab32dac5b1c13, retrieved 2026-10-07, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF