component

TFP401APZP

Public Made by Adom

by adom

Texas Instruments Video Interface ICs, TQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentinterfacetfp401apzpfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
tfp401apzp / README.md
History Download
Ray Initial commit: component/tfp401apzp 1be58a4 18h ago

TFP401APZP

Texas Instruments · Video Interface ICs · TQFP-100(14x14)

TFP401APZP from Texas Instruments, in a TQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DFO input Output clock data format control: continuous for TFT mode (low) or gated by DE for DSTN mode (high)
2 PD input Active-low power-down control for all analog circuits and output buffers
3 ST input Output drive strength select: high-drive (high) or low-drive (low)
4 PIXS input Pixel select: 1-pixel/clock mode (low) or 2-pixels/clock mode (high)
5 DGND power_in Digital ground reference and current return for digital core
6 DVDD power_out Digital supply voltage nominally 3.3V for digital core
7 STAG input Active-low staggered pixel output select to reduce ground bounce in 2-pixel/clock mode
8 SCDT output Sync detect output: high for active link when DE switches, low for inactive link
9 PDO input Active-low output driver power-down control
10 QE0 output Even blue-pixel output LSB synchronized to ODCK
11 QE1 output Even blue-pixel output synchronized to ODCK
12 QE2 output Even blue-pixel output synchronized to ODCK
13 QE3 output Even blue-pixel output synchronized to ODCK
14 QE4 output Even blue-pixel output synchronized to ODCK
15 QE5 output Even blue-pixel output synchronized to ODCK
16 QE6 output Even blue-pixel output synchronized to ODCK
17 QE7 output Even blue-pixel output MSB synchronized to ODCK
18 OVDD power_out Output driver supply voltage nominally 3.3V
19 OGND power_in Output driver ground reference and current return
20 QE8 output Even green-pixel output LSB synchronized to ODCK
21 QE9 output Even green-pixel output synchronized to ODCK
22 QE10 output Even green-pixel output synchronized to ODCK
23 QE11 output Even green-pixel output synchronized to ODCK
24 QE12 output Even green-pixel output synchronized to ODCK
25 QE13 output Even green-pixel output synchronized to ODCK
26 QE14 output Even green-pixel output synchronized to ODCK
27 QE15 output Even green-pixel output MSB synchronized to ODCK
28 OGND power_in Output driver ground reference and current return
29 OVDD power_out Output driver supply voltage nominally 3.3V
30 QE16 output Even red-pixel output LSB synchronized to ODCK
31 QE17 output Even red-pixel output synchronized to ODCK
32 QE18 output Even red-pixel output synchronized to ODCK
33 QE19 output Even red-pixel output synchronized to ODCK
34 QE20 output Even red-pixel output synchronized to ODCK
35 QE21 output Even red-pixel output synchronized to ODCK
36 QE22 output Even red-pixel output synchronized to ODCK
37 QE23 output Even red-pixel output MSB synchronized to ODCK
38 DVDD power_out Digital supply voltage nominally 3.3V for digital core
39 DGND power_in Digital ground reference and current return for digital core
40 CTL1 output General-purpose control signal; not powered down via PDO
41 CTL2 output General-purpose control signal used for user-defined control
42 CTL3 output General-purpose control signal used for user-defined control
43 OVDD power_out Output driver supply voltage nominally 3.3V
44 ODCK output Output data clock (pixel clock) synchronizing all pixel outputs and control signals
45 OGND power_in Output driver ground reference and current return
46 DE output Output data enable: high during active video display, low during blank time
47 VSYNC output Vertical sync output signal
48 HSYNC output Horizontal sync output signal
49 QO0 output Odd blue-pixel output LSB for 2-pixel/clock mode, held low in 1-pixel/clock mode
50 QO1 output Odd blue-pixel output for 2-pixel/clock mode, held low in 1-pixel/clock mode
51 QO2 output Odd blue-pixel output for 2-pixel/clock mode, held low in 1-pixel/clock mode
52 QO3 output Odd blue-pixel output for 2-pixel/clock mode, held low in 1-pixel/clock mode
53 QO4 output Odd blue-pixel output for 2-pixel/clock mode, held low in 1-pixel/clock mode
54 QO5 output Odd blue-pixel output for 2-pixel/clock mode, held low in 1-pixel/clock mode
55 QO6 output Odd blue-pixel output for 2-pixel/clock mode, held low in 1-pixel/clock mode
56 QO7 output Odd blue-pixel output MSB for 2-pixel/clock mode, held low in 1-pixel/clock mode
57 OVDD power_out Output driver supply voltage nominally 3.3V
58 OGND power_in Output driver ground reference and current return
59 QO8 output Odd green-pixel output LSB for 2-pixel/clock mode, held low in 1-pixel/clock mode
60 QO9 output Odd green-pixel output for 2-pixel/clock mode, held low in 1-pixel/clock mode
61 QO10 output Odd green-pixel output for 2-pixel/clock mode, held low in 1-pixel/clock mode
62 QO11 output Odd green-pixel output for 2-pixel/clock mode, held low in 1-pixel/clock mode
63 QO12 output Odd green-pixel output for 2-pixel/clock mode, held low in 1-pixel/clock mode
64 QO13 output Odd green-pixel output for 2-pixel/clock mode, held low in 1-pixel/clock mode
65 QO14 output Odd green-pixel output for 2-pixel/clock mode, held low in 1-pixel/clock mode
66 QO15 output Odd green-pixel output MSB for 2-pixel/clock mode, held low in 1-pixel/clock mode
67 DVDD power_out Digital supply voltage nominally 3.3V for digital core
68 DGND power_in Digital ground reference and current return for digital core
69 QO16 output Odd red-pixel output LSB for 2-pixel/clock mode, held low in 1-pixel/clock mode
70 QO17 output Odd red-pixel output for 2-pixel/clock mode, held low in 1-pixel/clock mode
71 QO18 output Odd red-pixel output for 2-pixel/clock mode, held low in 1-pixel/clock mode
72 QO19 output Odd red-pixel output for 2-pixel/clock mode, held low in 1-pixel/clock mode
73 QO20 output Odd red-pixel output for 2-pixel/clock mode, held low in 1-pixel/clock mode
74 QO21 output Odd red-pixel output for 2-pixel/clock mode, held low in 1-pixel/clock mode
75 QO22 output Odd red-pixel output for 2-pixel/clock mode, held low in 1-pixel/clock mode
76 OGND power_in Output driver ground reference and current return
77 QO23 output Odd red-pixel output MSB for 2-pixel/clock mode, held low in 1-pixel/clock mode
78 OVDD power_out Output driver supply voltage nominally 3.3V
79 AGND power_in Analog ground reference and current return for analog circuitry
80 Rx2+ input Channel-2 positive receiver input (red pixel data), TMDS low-voltage signal differential input
81 Rx2- input Channel-2 negative receiver input (red pixel data), TMDS low-voltage signal differential input
82 AVDD power_out Analog supply voltage nominally 3.3V for analog circuitry
83 AGND power_in Analog ground reference and current return for analog circuitry
84 AVDD power_out Analog supply voltage nominally 3.3V for analog circuitry
85 Rx1+ input Channel-1 positive receiver input (green pixel data), TMDS low-voltage signal differential input
86 Rx1- input Channel-1 negative receiver input (green pixel data), TMDS low-voltage signal differential input
87 AGND power_in Analog ground reference and current return for analog circuitry
88 AVDD power_out Analog supply voltage nominally 3.3V for analog circuitry
89 AGND power_in Analog ground reference and current return for analog circuitry
90 Rx0+ input Channel-0 positive receiver input (blue pixel data), TMDS low-voltage signal differential input
91 Rx0- input Channel-0 negative receiver input (blue pixel data), TMDS low-voltage signal differential input
92 AGND power_in Analog ground reference and current return for analog circuitry
93 RxC+ input Clock positive receiver input, TMDS low-voltage signal differential input pair
94 RxC- input Clock negative receiver input, TMDS low-voltage signal differential input pair
95 AVDD power_out Analog supply voltage nominally 3.3V for analog circuitry
96 EXT_RES input Internal impedance matching reference; device internally optimized for 50Ω impedance
97 PVDD power_out PLL supply voltage for internal PLL
98 PGND power_in PLL ground reference and current return for internal PLL
99 RSVD input Reserved pin; must be tied high for normal operation
100 OCK_INV input ODCK polarity select: latches data on rising edge (high) or falling edge (low) of ODCK

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TQFP-100(14x14)
Category Interface
Pins 100

CAD (KiCad official)

  • Symbol: TFP401APZP
  • Footprint: Package_QFP:TQFP-100_14x14mm_P0.5mm
  • 3D model: TQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: tfp401apzp-etched.step / tfp401apzp-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tfp401apzp.step / tfp401apzp.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (37 pp, sha256 4faebec02402e979, retrieved 2026-10-05, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF