component
TDC7200PW
Public Made by Adomby adom
Texas Instruments ADCs/DACs - Special Purpose, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTDC7200PW
Texas Instruments · ADCs/DACs - Special Purpose · TSSOP-14
TDC7200PW from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ENABLE | input | Enable signal to TDC; positive edge required after power-up to initialize all digital circuits. |
| 2 | TRIGG | output | Trigger output signal; generated after START_MEAS command to initiate measurement in analog front-end. |
| 3 | START | input | START pulse input marking measurement start; trigger edge selectable via START_EDGE configuration bit. |
| 4 | STOP | input | STOP pulse input for echo detection; up to 5 signals supported with selectable trigger edge via STOP_EDGE bit. |
| 5 | CLOCK | input | Reference clock input with frequency range 1 to 16 MHz used for internal time base calibration. |
| 6 | N.C. | unconnected | Not connected. |
| 7 | GND | power_in | Ground; provides circuit return and signal reference at 0 V. |
| 8 | INTB | tri_state | Interrupt output to MCU, active low open-drain; asserts on measurement completion or counter overflow conditions. |
| 9 | DOUT | tri_state | SPI data output driven during read transactions; enters high impedance state when not being read. |
| 10 | DIN | input | SPI data input; receives configuration and register access commands from master device. |
| 11 | CSB | input | SPI chip select bar, active low; must remain low throughout a complete SPI transaction. |
| 12 | SCLK | input | SPI clock input; supports frequencies up to 20 MHz per timing specifications. |
| 13 | VREG | power_out | LDO output terminal for internal analog circuits; requires 0.4 to 2.7 µF external ceramic decoupling capacitor. |
| 14 | VDD | power_in | Power supply input; operating voltage range 2.0 V to 3.6 V per specifications. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-14 |
| Category | Data Acquisition |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
TDC7200PW - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
tdc7200pw-etched.step/tdc7200pw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tdc7200pw.step/tdc7200pw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (52 pp, sha256
0a0accdd4231b23e, retrieved 2026-09-26, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).