component
TC4420EPA
Public Made by Adomby adom
Microchip Tech Gate Drivers, PDIP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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{
"slug": "tc4420epa",
"version": "0.1.0",
"type": "component",
"description": "Microchip Tech Gate Drivers, PDIP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"tags": [
"component",
"motor driver ics",
"tc4420epa",
"factory-2.0.0",
"extractor-text"
],
"dependencies": {},
"hero": {
"type": "image",
"path": "docs/hero.png"
},
"files": [
"page.json",
"README.md",
"tc4420epa.kicad_sym",
"tc4420epa.kicad_mod",
"tc4420epa.glb",
"tc4420epa.step",
"tc4420epa.lbr",
"docs/hero.png",
"docs/tc4420epa-datasheet.pdf",
"viewers/symbol.html",
"viewers/footprint.html",
"tc4420epa-hero.glb",
"tc4420epa-hero.overlay.json",
"tc4420epa-etched.glb"
],
"component": {
"mpn": "TC4420EPA",
"manufacturer": "Microchip Tech",
"package": "PDIP-8",
"pin_count": 8,
"category": "Motor Driver ICs",
"subcategory": "Gate Drivers",
"datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588906018524286976",
"parts": {
"symbol": "tc4420epa.kicad_sym",
"footprint": "tc4420epa.kicad_mod",
"model_3d": "tc4420epa-hero.glb",
"model_3d_plain": "tc4420epa-etched.glb",
"model_3d_step": "tc4420epa-etched.step",
"model_3d_step_plain": "tc4420epa.step",
"lbr": "tc4420epa.lbr"
},
"distributor_links": {
"lcsc": "C640742",
"digikey": "TC4420EPA-ND",
"mouser": "579-TC4420EPA"
},
"distributor_check": {
"checked_at": "2026-10-15T21:26:11Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": "TC4420EPA-ND",
"status": "found",
"lifecycle": "Active"
},
"mouser": {
"pn": "579-TC4420EPA",
"status": "found"
}
},
"pins": [
{
"number": "1",
"name": "VDD",
"type": "power_in",
"description": "Bias supply for the MOSFET driver, rated 4.5V to 18V with respect to the ground pins, and should be bypassed to ground with a local ceramic capacitor (minimum 1.0 µF suggested)."
},
{
"number": "2",
"name": "INPUT",
"type": "input",
"description": "High-impedance, TTL/CMOS compatible control input that can be driven from -5V up to VDD + 0.3V, and slow rising or falling input edges should be avoided to prevent double-pulsing of the output."
},
{
"number": "3",
"name": "NC",
"type": "unconnected",
"description": "No connection."
},
{
"number": "4",
"name": "GND",
"type": "power_in",
"description": "Ground return path for the bias current and high peak discharge currents of the load capacitor, to be tied to a ground plane or kept on very short traces; both GND pins must be connected for proper operation."
},
{
"number": "5",
"name": "GND",
"type": "power_in",
"description": "Ground return path for the bias current and high peak discharge currents of the load capacitor, to be tied to a ground plane or kept on very short traces; both GND pins must be connected for proper operation."
},
{
"number": "6",
"name": "OUTPUT",
"type": "output",
"description": "CMOS push-pull output capable of 6.0A peak sourcing/sinking current into a capacitive load and withstanding 1.5A peak reverse current of either polarity; both OUTPUT pins must be connected for proper operation."
},
{
"number": "7",
"name": "OUTPUT",
"type": "output",
"description": "CMOS push-pull output capable of 6.0A peak sourcing/sinking current into a capacitive load and withstanding 1.5A peak reverse current of either polarity; both OUTPUT pins must be connected for proper operation."
},
{
"number": "8",
"name": "VDD",
"type": "power_in",
"description": "Supply input, rated 4.5V to 18V with respect to the ground pins; both VDD pins must be connected for proper operation."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: The datasheet has no ordering example for TC4420EPA. The PA suffix is listed in the Product Identifi; Table 3-1 gives the PDIP/SOIC/CERDIP pin assignment, and page 9 confirms the pinout applies to the P"
],
"pages_sent": 22,
"cost_usd": 0.0765,
"at": "2026-10-15T21:25:58"
},
"datasheet": {
"url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588906018524286976",
"pages": 22,
"sha256": "242021ee5290b9d9",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 8,
"described": 8,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
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"footprint": "viewers/footprint.html"
},
"models_3d": [
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"file": "tc4420epa.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "body on z = 0, through-hole leads below",
"extents_mm": [
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],
"zmin_mm": -3.3,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "4a377a56a8d9e9c0b86c095ef9ecc1869ac19e7f5069a3247b294250bf4f235d",
"checked": "2026-10-15",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "tc4420epa-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "body on z = 0, through-hole leads below",
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"footprint_binding": "identity",
"sha256": "4fe737d5eb55b283d6f598fef35cdf4425f0685d091f18faf71d7561c185119f",
"checked": "2026-10-15",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
]
}
}