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TC4420EPA
Public Made by Adomby adom
Microchip Tech Gate Drivers, PDIP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTC4420EPA
Microchip Tech · Gate Drivers · PDIP-8
TC4420EPA from Microchip Tech, in a PDIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Bias supply for the MOSFET driver, rated 4.5V to 18V with respect to the ground pins, and should be bypassed to ground with a local ceramic capacitor (minimum 1.0 µF suggested). |
| 2 | INPUT | input | High-impedance, TTL/CMOS compatible control input that can be driven from -5V up to VDD + 0.3V, and slow rising or falling input edges should be avoided to prevent double-pulsing of the output. |
| 3 | NC | unconnected | No connection. |
| 4 | GND | power_in | Ground return path for the bias current and high peak discharge currents of the load capacitor, to be tied to a ground plane or kept on very short traces; both GND pins must be connected for proper operation. |
| 5 | GND | power_in | Ground return path for the bias current and high peak discharge currents of the load capacitor, to be tied to a ground plane or kept on very short traces; both GND pins must be connected for proper operation. |
| 6 | OUTPUT | output | CMOS push-pull output capable of 6.0A peak sourcing/sinking current into a capacitive load and withstanding 1.5A peak reverse current of either polarity; both OUTPUT pins must be connected for proper operation. |
| 7 | OUTPUT | output | CMOS push-pull output capable of 6.0A peak sourcing/sinking current into a capacitive load and withstanding 1.5A peak reverse current of either polarity; both OUTPUT pins must be connected for proper operation. |
| 8 | VDD | power_in | Supply input, rated 4.5V to 18V with respect to the ground pins; both VDD pins must be connected for proper operation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | PDIP-8 |
| Category | Motor Driver ICs |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Logic '1', High Input Voltage | VIH | 2.4 | 1.8 | V | TA = +25°C, 4.5V ≤ VDD ≤ 18V | 3 | |
| Logic '0', Low Input Voltage | VIL | 1.3 | 0.8 | V | TA = +25°C, 4.5V ≤ VDD ≤ 18V | 3 | |
| Input Voltage Range | VIN | -5 | V | TA = +25°C, 4.5V ≤ VDD ≤ 18V | 3 | ||
| Input Current | IIN | -10 | 10 | µA | 0V ≤ VIN ≤ VDD | 3 | |
| Low Output Voltage | VOL | 0.025 | V | DC TEST | 3 | ||
| Output Resistance, High | ROH | 2.1 | 2.8 | Ω | IOUT = 10 mA, VDD = 18V | 3 | |
| Output Resistance, Low | ROL | 1.5 | 2.5 | Ω | IOUT = 10 mA, VDD = 18V | 3 | |
| Latch-Up Protection Withstand Reverse Current | IREV | 1.5 | A | Duty cycle ≤2%, t ≤300 µsec | 3 | ||
| Rise Time | tR | 25 | 35 | ns | Figure 4-1, CL = 2,500 pF | 3 | |
| Fall Time | tF | 25 | 35 | ns | Figure 4-1, CL = 2,500 pF | 3 | |
| Delay Time tD1 | tD1 | 55 | 75 | ns | Figure 4-1 | 3 | |
| Delay Time tD2 | tD2 | 55 | 75 | ns | Figure 4-1 | 3 | |
| Power Supply Current | IS | 0.45 | 1.5 | mA | VIN = 3V | 3 | |
| Power Supply Current | IS | 55 | 150 | µA | VIN = 0V | 3 | |
| Operating Input Voltage | VDD | 4.5 | 18 | V | TA = +25°C | 3 | |
| Logic '1', High Input Voltage | VIH | 2.4 | V | over operating temperature range | 4 | ||
| Logic '0', Low Input Voltage | VIL | 0.8 | V | over operating temperature range | 4 | ||
| Input Voltage Range | VIN | -5 | V | over operating temperature range | 4 | ||
| Input Current | IIN | -10 | 10 | µA | 0V ≤ VIN ≤ VDD | 4 | |
| Low Output Voltage | VOL | 0.025 | V | DC TEST | 4 | ||
| Output Resistance, Low | ROL | 2.3 | 5 | Ω | IOUT = 10 mA, VDD = 18V | 4 | |
| Rise Time | tR | 32 | 60 | ns | Figure 4-1, CL = 2,500 pF | 4 | |
| Fall Time | tF | 34 | 60 | ns | Figure 4-1, CL = 2,500 pF | 4 | |
| Delay Time tD1 | tD1 | 50 | 100 | ns | Figure 4-1 | 4 | |
| Delay Time tD2 | tD2 | 65 | 100 | ns | Figure 4-1 | 4 | |
| Power Supply Current | IS | 0.45 | 3 | mA | VIN = 3V | 4 | |
| Power Supply Current | IS | 60 | 400 | µA | VIN = 0V | 4 | |
| Operating Input Voltage | VDD | 4.5 | 18 | V | over operating temperature range | 4 | |
| Specified Temperature Range (E) | TA | -40 | 85 | °C | 4 | ||
| Storage Temperature Range | TA | -65 | 150 | °C | 4 | ||
| Maximum Junction Temperature | TJ | 150 | °C | 4 | |||
| Supply Voltage | VDD | 20 | V | 3 | |||
| Input Voltage | -5 | V | 3 | ||||
| Input Current | 50 | mA | VIN > VDD | 3 | |||
| Thermal Resistance, 8L-PDIP | JA | 125 | °C/W | 4 | |||
| Peak Output Current | IPK | 6 | A | VDD = 18V | 3 |
CAD (KiCad official)
- Symbol:
TC4420EPA - Footprint:
Package_DIP:DIP-8_W7.62mm - 3D model: PDIP-8 (KiCad packages3D, STEP)
- 3D model files:
tc4420epa-etched.step/tc4420epa-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tc4420epa.step/tc4420epa.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (22 pp, sha256
242021ee5290b9d9, retrieved 2026-10-15, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).