component
SY8213FCC
Public Made by Adomby adom
Silergy Corp DC-DC Converters, SOIC-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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"slug": "sy8213fcc",
"title": "SY8213FCC",
"brief": "Silergy Corp DC-DC Converters, SOIC-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"version": "0.1.0",
"license": "CC-BY-SA-4.0",
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"package": "SOIC-8-EP",
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"category": "Power Management (PMIC)",
"subcategory": "DC-DC Converters",
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},
{
"number": "2",
"name": "LX",
"type": "power_out",
"description": "Inductor pin; connect to the switching node of the inductor."
},
{
"number": "3",
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"description": "Enable control; pulling low (<1.2V) shuts the device down and driving high (>1.3V) turns it on."
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{
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"type": "passive",
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{
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"description": "Output feedback pin; connect to the center point of the output resistor divider, Vout=0.6*(1+R1/R2)."
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{
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{
"number": "7",
"name": "SVIN",
"type": "power_in",
"description": "Analog supply input; bypass with a 1uF capacitor to ground."
},
{
"number": "8",
"name": "PVIN",
"type": "power_in",
"description": "Power supply input (4.5V to 30V); decouple to GND with at least 10uF ceramic capacitor."
},
{
"number": "9",
"name": "GND",
"type": "power_in",
"description": "Ground pin on the exposed paddle; maximize PCB copper area connected to it for thermal and noise performance."
}
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"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: The datasheet lists GND as the exposed paddle with no printed pin number, so it is not included in t; The datasheet gives no explicit ERC class for these pins; BS is typed power_in (gate-driver supply) ; The 4.5V to 30V range is stated in the recommended operating conditions for the supply input, and th",
"exposed pad 9 added from the footprint"
],
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"cost_usd": 0.0349,
"at": "2026-10-18T07:27:54"
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"sha256": "fe04792090409c80",
"source_tier": "lcsc"
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"cad": "KiCad official (CC-BY-SA 4.0)",
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"metadata": {
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"Package": "SOIC-8-EP",
"Category": "Power Management (PMIC)",
"Pins": "9"
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"appearance": {
"contacts": {
"quote": "ground plane is highly desirable. 2) CINmust be close to IN and GND Pins. The loop area formed by CIN and GND must be minimized. 3) The PCB copper area associated with LX pin must",
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"material": "copper"
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{
"name": "Feedback Reference Voltage",
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{
"name": "Junction Temperature Range (absolute maximum)",
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{
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{
"name": "Lead Temperature (Soldering)",
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"name": "Supply Input Voltage",
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"min": -40,
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{
"name": "Ambient Temperature Range",
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"unit": "°C",
"min": -40,
"typ": null,
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"conditions": "",
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{
"name": "Top FET RON",
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"unit": "mΩ",
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"min": null,
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{
"name": "Bottom FET Current Limit",
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{
"name": "EN threshold hysteresis",
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{
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{
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{
"name": "Oscillator Frequency",
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"min": null,
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{
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{
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{
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{
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"min": null,
"typ": 20,
"max": null,
"conditions": "",
"source_page": 3,
"source": "datasheet"
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{
"name": "Package Thermal Resistance junction-to-ambient",
"symbol": "θJA",
"kind": "thermal",
"unit": "°C/W",
"min": null,
"typ": 30,
"max": null,
"conditions": "",
"source_page": 2,
"source": "datasheet"
},
{
"name": "Package Thermal Resistance junction-to-case",
"symbol": "θJC",
"kind": "thermal",
"unit": "°C/W",
"min": null,
"typ": 10,
"max": null,
"conditions": "",
"source_page": 2,
"source": "datasheet"
}
]
}
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