component
SY8213FCC
Public Made by Adomby adom
Silergy Corp DC-DC Converters, SOIC-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Contents
README
markdownSY8213FCC
Silergy Corp · DC-DC Converters · SOIC-8-EP
SY8213FCC from Silergy Corp, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BS | passive | Boot-strap pin supplying the high side gate driver; decouple to the LX pin with a 0.1uF ceramic capacitor. |
| 2 | LX | power_out | Inductor pin; connect to the switching node of the inductor. |
| 3 | EN | input | Enable control; pulling low (<1.2V) shuts the device down and driving high (>1.3V) turns it on. |
| 4 | SS | passive | Softstart programming pin; connect a capacitor to ground, Tss(ms)=Css(nF)*0.6(V)/10(uA). |
| 5 | FB | input | Output feedback pin; connect to the center point of the output resistor divider, Vout=0.6*(1+R1/R2). |
| 6 | VCC | power_out | Internal 3.3V LDO output powering internal analog and driving circuits; add a 1uF bypass capacitor to GND (sources up to 20mA). |
| 7 | SVIN | power_in | Analog supply input; bypass with a 1uF capacitor to ground. |
| 8 | PVIN | power_in | Power supply input (4.5V to 30V); decouple to GND with at least 10uF ceramic capacitor. |
| 9 | GND | power_in | Ground pin on the exposed paddle; maximize PCB copper area connected to it for thermal and noise performance. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Silergy Corp |
| Package | SOIC-8-EP |
| Category | Power Management (PMIC) |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage Range | VIN | 4.5 | 30 | V | 3 | ||
| Quiescent Current | IQ | 200 | µA | IOUT=0, VFB=VREF*105% | 3 | ||
| Shutdown Current | ISHDN | 10 | µA | EN=0 | 3 | ||
| Feedback Reference Voltage | VREF | 0.591 | 0.6 | 0.609 | V | 3 | |
| FB Input Current | IFB | -50 | 50 | nA | VFB=VCC | 3 | |
| EN falling threshold | VENL | 1.1 | 1.2 | 1.3 | V | 3 | |
| Internal LDO Output | VVCC | 3.2 | 3.3 | 3.4 | V | VIN=4V | 3 |
| Power Dissipation | PD | 3.3 | W | @ TA = 25°C, SO8E | 2 | ||
| Junction Temperature Range (absolute maximum) | -40 | 150 | °C | 2 | |||
| Storage Temperature Range | -65 | 150 | °C | 2 | |||
| Lead Temperature (Soldering) | 260 | °C | Soldering, 10 sec. | 2 | |||
| Supply Input Voltage | 4.5 | 30 | V | 2 | |||
| Junction Temperature Range (recommended) | -40 | 125 | °C | 2 | |||
| Ambient Temperature Range | -40 | 85 | °C | 2 | |||
| Top FET RON | RDS(ON)1 | 90 | mΩ | 3 | |||
| Bottom FET RON | RDS(ON)2 | 60 | mΩ | 3 | |||
| Bottom FET Current Limit | ILIM | 4 | A | 3 | |||
| EN threshold hysteresis | VEN,HYS | 0.1 | V | 3 | |||
| Input UVLO threshold | VUVLO | 4 | V | 3 | |||
| UVLO hysteresis | VHYS | 0.2 | V | 3 | |||
| Oscillator Frequency | FOSC | 0.5 | MHz | IOUT=200mA | 3 | ||
| Min ON Time | 80 | ns | 3 | ||||
| Min OFF Time | 120 | ns | 3 | ||||
| Thermal Shutdown Temperature | TSD | 160 | °C | 3 | |||
| Thermal Shutdown Hysteresis | TSD,HYS | 20 | °C | 3 | |||
| Package Thermal Resistance junction-to-ambient | θJA | 30 | °C/W | 2 | |||
| Package Thermal Resistance junction-to-case | θJC | 10 | °C/W | 2 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | ground plane is highly desirable. 2) CINmust be close to IN and GND Pins. The loop area formed by CIN and GND must be minimized. 3) The PCB copper area associated with LX pin must | 8 |
CAD (KiCad official)
- Symbol:
SY8213FCC - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOIC-8-EP (KiCad packages3D, STEP)
- 3D model files:
sy8213fcc-etched.step/sy8213fcc-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sy8213fcc.step/sy8213fcc.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Silergy Corp datasheet (9 pp, sha256
fe04792090409c80, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).