component
SY8029AIC
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Silergy Corp DC-DC Converters, TSOT-23-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SY8029AIC
Silergy Corp · DC-DC Converters · TSOT-23-8
SY8029AIC from Silergy Corp, in a TSOT-23-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | FB1 | input | Feedback pin for output1; connect it to the center point of the output resistor divider to program VOUT1 = 0.6V*(1+RH1/RL1). |
| 2 | IN | power_in | Power input pin; decouple it to ground with at least 10uF ceramic capacitance. The input supply range is 2.5V to 5.5V. |
| 3 | LX1 | output | Inductor pin for output1; connect it to the switching node of the output1 inductor. |
| 4 | GND | power_in | Ground pins. |
| 5 | LX2 | output | Inductor pin for output2; connect it to the switching node of the output2 inductor. |
| 6 | EN2 | input | Enable pin for output2; do not leave it floating. |
| 7 | EN1 | input | Enable pin for output1; do not leave it floating. |
| 8 | FB2 | input | Feedback pin for output2; connect it to the center point of the output resistor divider to program VOUT2 = 0.6V*(1+RH2/RL2). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Silergy Corp |
| Package | TSOT-23-8 |
| Category | Power Management ICs |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage Range | VIN | 2.5 | 5.5 | V | 3 | ||
| Shutdown Current | ISHDN | 0.1 | 1 | µA | EN1=EN2=0 | 3 | |
| Quiescent Current | IQ | 35 | µA | EN1=1 or EN2=1, IOUT1= IOUT1=0, no switching | 3 | ||
| Quiescent Current | IQ | 45 | µA | EN1=1 and EN2=1, IOUT1= IOUT2=0, no switching | 3 | ||
| Feedback Reference Voltage | VREF1, VREF2 | 0.588 | 0.6 | 0.612 | V | 3 | |
| Supply Input Voltage | VIN | 2.5 | 5.5 | V | 2 | ||
| Power Dissipation | PD | 1.7 | W | TA = 25°C, TSOT23-8 | 2 | ||
| Junction Temperature Range | 150 | °C | 2 | ||||
| Lead Temperature (Soldering) | 260 | °C | Soldering, 10 sec. | 2 | |||
| Storage Temperature Range | 150 | °C | 2 | ||||
| Junction Temperature Range | 125 | °C | 2 | ||||
| Ambient Temperature Range | 85 | °C | 2 | ||||
| Input UVLO Threshold | VUVLO | 2.5 | V | 3 | |||
| UVLO Hysteresis | VHYS1 | 0.2 | V | 3 | |||
| Oscillator Frequency | fOSC | 2 | MHz | IOUT1 = 0.1A, IOUT2 = 0.1A | 3 | ||
| Thermal Shutdown Temperature | TSD | 150 | °C | 3 | |||
| Thermal Shutdown Hysteresis | THYS | 20 | °C | 3 | |||
| PFET RON | RDS(ON),P1, RDS(ON),P2 | 125 | mΩ | 3 | |||
| NFET RON | RDS(ON),N1, RDS(ON),N2 | 100 | mΩ | 3 | |||
| PFET Current Limit | ILIM1, ILIM2 | 2.8 | A | 3 | |||
| EN Rising Threshold | VENH1, VENH2 | 1.2 | V | 3 | |||
| EN Falling Threshold | VENL1, VENL2 | 0.4 | V | 3 | |||
| Internal Soft Start Time | tSS1, tSS2 | 1 | ms | 3 | |||
| Package Thermal Resistance junction-to-ambient | θJA | 60 | °C/W | Natural convection at TA = 25°C, JEDEC 51-3 low effective single layer board | 2 | ||
| Package Thermal Resistance junction-to-case | θJC | 15 | °C/W | 2 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | enhance the soldering quality and thermal performance. 2) Input cap must be close to Pins IN and GND. The loop area formed by input cap , IN, GND must be minimized. 3) The PCB copper area associated w | 7 |
CAD (KiCad official)
- Symbol:
SY8029AIC - Footprint:
Package_TO_SOT_SMD:TSOT-23-8 - 3D model: TSOT-23-8 (KiCad packages3D, STEP)
- 3D model files:
sy8029aic-etched.step/sy8029aic-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sy8029aic.step/sy8029aic.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Silergy Corp datasheet (9 pp, sha256
fbf59f059404a3a1, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SY8029AIC
**Silergy Corp** · DC-DC Converters · TSOT-23-8
SY8029AIC from Silergy Corp, in a TSOT-23-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | FB1 | input | Feedback pin for output1; connect it to the center point of the output resistor divider to program VOUT1 = 0.6V*(1+RH1/RL1). |
| 2 | IN | power_in | Power input pin; decouple it to ground with at least 10uF ceramic capacitance. The input supply range is 2.5V to 5.5V. |
| 3 | LX1 | output | Inductor pin for output1; connect it to the switching node of the output1 inductor. |
| 4 | GND | power_in | Ground pins. |
| 5 | LX2 | output | Inductor pin for output2; connect it to the switching node of the output2 inductor. |
| 6 | EN2 | input | Enable pin for output2; do not leave it floating. |
| 7 | EN1 | input | Enable pin for output1; do not leave it floating. |
| 8 | FB2 | input | Feedback pin for output2; connect it to the center point of the output resistor divider to program VOUT2 = 0.6V*(1+RH2/RL2). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Silergy Corp |
| Package | TSOT-23-8 |
| Category | Power Management ICs |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage Range | VIN | 2.5 | | 5.5 | V | | 3 |
| Shutdown Current | ISHDN | | 0.1 | 1 | µA | EN1=EN2=0 | 3 |
| Quiescent Current | IQ | | | 35 | µA | EN1=1 or EN2=1, IOUT1= IOUT1=0, no switching | 3 |
| Quiescent Current | IQ | | | 45 | µA | EN1=1 and EN2=1, IOUT1= IOUT2=0, no switching | 3 |
| Feedback Reference Voltage | VREF1, VREF2 | 0.588 | 0.6 | 0.612 | V | | 3 |
| Supply Input Voltage | VIN | 2.5 | | 5.5 | V | | 2 |
| Power Dissipation | PD | | | 1.7 | W | TA = 25°C, TSOT23-8 | 2 |
| Junction Temperature Range | | | | 150 | °C | | 2 |
| Lead Temperature (Soldering) | | | | 260 | °C | Soldering, 10 sec. | 2 |
| Storage Temperature Range | | | | 150 | °C | | 2 |
| Junction Temperature Range | | | | 125 | °C | | 2 |
| Ambient Temperature Range | | | | 85 | °C | | 2 |
| Input UVLO Threshold | VUVLO | | 2.5 | | V | | 3 |
| UVLO Hysteresis | VHYS1 | | 0.2 | | V | | 3 |
| Oscillator Frequency | fOSC | | 2 | | MHz | IOUT1 = 0.1A, IOUT2 = 0.1A | 3 |
| Thermal Shutdown Temperature | TSD | | 150 | | °C | | 3 |
| Thermal Shutdown Hysteresis | THYS | | 20 | | °C | | 3 |
| PFET RON | RDS(ON),P1, RDS(ON),P2 | | 125 | | mΩ | | 3 |
| NFET RON | RDS(ON),N1, RDS(ON),N2 | | 100 | | mΩ | | 3 |
| PFET Current Limit | ILIM1, ILIM2 | | 2.8 | | A | | 3 |
| EN Rising Threshold | VENH1, VENH2 | | 1.2 | | V | | 3 |
| EN Falling Threshold | VENL1, VENL2 | | 0.4 | | V | | 3 |
| Internal Soft Start Time | tSS1, tSS2 | | 1 | | ms | | 3 |
| Package Thermal Resistance junction-to-ambient | θJA | | 60 | | °C/W | Natural convection at TA = 25°C, JEDEC 51-3 low effective single layer board | 2 |
| Package Thermal Resistance junction-to-case | θJC | | 15 | | °C/W | | 2 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | | enhance the soldering quality and thermal performance. 2) Input cap must be close to Pins IN and GND. The loop area formed by input cap , IN, GND must be minimized. 3) The PCB copper area associated w | 7 |
## CAD (KiCad official)
- Symbol: `SY8029AIC`
- Footprint: `Package_TO_SOT_SMD:TSOT-23-8`
- 3D model: TSOT-23-8 (KiCad packages3D, STEP)
- 3D model files: `sy8029aic-etched.step` / `sy8029aic-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sy8029aic.step` / `sy8029aic.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Silergy Corp datasheet](docs/sy8029aic-datasheet.pdf) (9 pp, sha256 `fbf59f059404a3a1`, retrieved 2026-11-05, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sy8029aic-datasheet.pdf)