# SY6874DBC

**Silergy Corp** · Power Distribution Switches · DFN-10-EP(3x3)

SY6874DBC from Silergy Corp, in a DFN-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | power_in | Power input pin; decouple high-frequency noise by connecting at least 0.1uF MLCC to ground. |
| 2 | IN | power_in | Power input pin; decouple high-frequency noise by connecting at least 0.1uF MLCC to ground. |
| 3 | IN | power_in | Power input pin; decouple high-frequency noise by connecting at least 0.1uF MLCC to ground. |
| 4 | VCP | passive | Output clamp voltage selection based on input voltage: a resistor to IN selects High (3.3V/5V/12V mode per table), a resistor to ground selects Low, or floating selects Open; recommended decoupling with 0.1uF capacitor. |
| 5 | ILIM | passive | Current limit program pin; program the current limit by connecting a resistor to ground. |
| 6 | SST | passive | Soft-start time program pin; connect a capacitor to ground to program the soft-start time. |
| 7 | EN | input | Enable interface pin; pull it high to enable the IC. |
| 8 | OUT | power_out | Power output pin. |
| 9 | OUT | power_out | Power output pin. |
| 10 | OUT | power_out | Power output pin. |
| 11 | GND | power_in | Ground pin; this is the exposed paddle of the DFN package. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Silergy Corp |
| Package | DFN-10-EP(3x3) |
| Category | Power Management (PMIC) |
| Pins | 11 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Input Voltage |  |  |  | 30 | V |  | 3 |
| EN pin, VCP pin |  |  |  | 30 | V |  | 3 |
| Power Dissipation DFN3X3-10 | PD |  |  | 2.6 | W | TA = 25°C | 3 |
| Junction Temperature Range |  |  |  | 125 | °C |  | 3 |
| Lead Temperature (Soldering) |  |  |  | 260 | °C | Soldering, 10 sec. | 3 |
| Storage Temperature Range |  | -65 |  | 150 | °C |  | 3 |
| Thermal Resistance Junction-to-Ambient | θJA |  | 38 |  | °C/W | Natural convection, TA = 25°C, JEDEC 51-3 test board | 3 |
| Thermal Resistance Junction-to-Case | θJC |  | 8 |  | °C/W |  | 3 |
| Supply Input Voltage |  | 2.5 |  | 15 | V |  | 3 |
| Junction Temperature Range |  | -40 |  | 125 | °C |  | 3 |
| Ambient Temperature Range |  | -40 |  | 85 | °C |  | 3 |
| Input Voltage Range | VIN | 2.5 |  | 30 | V |  | 3 |
| Input UVLO Threshold | VUVLO | 2.2 |  | 2.4 | V | VCP=LOW | 3 |
| Input UVLO Threshold | VUVLO | 3.4 |  | 3.8 | V | VCP=HIGH | 3 |
| Input UVLO Threshold | VUVLO | 8.1 |  | 9 | V | VCP=OPEN | 3 |
| UVLO hysteresis | VHYS | 0.05 | 0.085 | 0.13 | V | VCP=LOW | 3 |
| UVLO hysteresis | VHYS | 0.06 | 0.095 | 0.15 | V | VCP=HIGH | 3 |
| UVLO hysteresis | VHYS | 0.1 | 0.19 | 0.29 | V | VCP=OPEN | 3 |
| Bias Current | IBIAS |  | 200 |  | µA |  | 3 |
| Shutdown Current | ISHDN |  | 10 |  | µA | EN=0 | 3 |
| Protection FET RON | RDS(ON) |  | 50 | 80 | mΩ |  | 3 |
| Current Limit Accuracy |  | -30 |  | 30 | % | Of ILIM | 3 |
| Current Limit Program Range | ILIM | 1 |  | 4 | A |  | 3 |
| Clamping Output Voltage | VCLP | 3.6 | 3.8 | 4 | V | VCP=LOW | 3 |
| Clamping Output Voltage | VCLP | 5.4 | 5.7 | 6 | V | VCP=HIGH | 3 |
| Clamping Output Voltage | VCLP | 12.6 | 13.3 | 14 | V | VCP=OPEN | 3 |
| Soft-start Time | TSST |  | 29.4 |  | ms | CSST=105nF | 3 |
| Soft-start Time Accuracy |  | -30 |  | 30 | % | Of TSST | 3 |
| EN Turn-on Threshold | VEN_ON |  | 2 |  | V |  | 3 |
| EN Turn-off Threshold | VEN_OFF |  | 0.4 |  | V |  | 3 |
| Thermal Shutdown Temperature | TSD |  | 140 |  | °C |  | 3 |
| Thermal Shutdown Hysteresis | THYS |  | 20 |  | °C |  | 3 |

## CAD (KiCad official)

- Symbol: `SY6874DBC`
- Footprint: `Package_DFN_QFN:DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm`
- 3D model: DFN-10-EP(3x3) (KiCad packages3D, STEP)
- 3D model files: `sy6874dbc-etched.step` / `sy6874dbc-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sy6874dbc.step` / `sy6874dbc.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Silergy Corp datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589834799797075969) (9 pp, sha256 `2905ad4b5488934b`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sy6874dbc-datasheet.pdf)