component
SY59119A1FCC
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Silergy Corp LED Drivers, SOP-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SY59119A1FCC
Silergy Corp · LED Drivers · SOP-8-EP
SY59119A1FCC from Silergy Corp, in a SOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | LX2 | passive | Drain of the bleeding MOS; the absolute maximum rating for LX2 is -0.3 V to 700 V (page 3). |
| 2 | HVCC | power_in | High-voltage power supply pin; the absolute maximum rating for HVCC is -0.3 V to 700 V (page 3). |
| 3 | NC | unconnected | No connect. |
| 4 | LX1 | passive | Drain of the main MOS; the absolute maximum rating for LX1 is -0.3 V to 500 V (page 3). |
| 5 | TFB | passive | Thermal foldback setting pin, set by a resistor from the datasheet TFB table (RTFB); the absolute maximum rating is -0.3 V to 3.6 V (page 3). |
| 6 | ISEN1 | input | Main MOS current sense pin used to set the output current together with ISEN2; the absolute maximum rating is -0.3 V to 3.6 V (page 3). |
| 7 | ISEN2 | input | BLD MOS current sense pin used to adjust the latching current via RISEN2, with a recommended value RISEN2 > 0.7 ohm; the absolute maximum rating is -0.3 V to 3.6 V (page 3). |
| 8 | VCC | power_in | Power supply pin; the absolute maximum rating for VCC is -0.3 V to 22 V (page 3). |
| 9 | GND | power_in | Ground reference pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Silergy Corp |
| Package | SOP-8-EP |
| Category | LED Drivers |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN Turn-on Threshold | VVIN_ON | 11 | 12.1 | 13.2 | V | 4 | |
| VIN Turn-off Threshold | VVIN_OFF | 7.8 | 8.8 | 9.8 | V | 4 | |
| Quiescent Current | IQ | 210 | 280 | 350 | µA | 4 | |
| Internal Reference Voltage | VREF | 0.291 | 0.3 | 0.309 | V | 4 | |
| Voltage on LX2, HVCC (absolute maximum) | -0.3 | 700 | V | 3 | |||
| Voltage on LX1 (absolute maximum) | -0.3 | 500 | V | 3 | |||
| Voltage on TFB, ISEN1, ISEN2 (absolute maximum) | -0.3 | 3.6 | V | 3 | |||
| Voltage on VCC (absolute maximum) | -0.3 | 22 | V | 3 | |||
| Power Dissipation SO8E | 3.3 | W | @ TA = 25°C, SO8E | 3 | |||
| Junction Temperature Range (absolute maximum) | -40 | 150 | °C | 3 | |||
| Lead Temperature (soldering) | 260 | °C | Soldering, 10 sec. | 3 | |||
| Storage Temperature Range | -65 | 150 | °C | 3 | |||
| Junction Temperature Range (recommended operating) | -40 | 150 | °C | 3 | |||
| Ambient Temperature Range (recommended operating) | -40 | 120 | °C | 3 | |||
| Clamped Current of LX1 MOS | ICLP | 32 | mA | 4 | |||
| BV of LX1 MOS | VBV_LX1 | 500 | V | 4 | |||
| BV of LX2 MOS | VBV_LX2 | 700 | V | 4 | |||
| Minimum Thermal Foldback Temperature | TFB1 | 115 | °C | 4 | |||
| Maximum Thermal Foldback Temperature | TFB2 | 155 | °C | 4 | |||
| Package Thermal Resistance Junction-to-Ambient SO8E | θJA | 30 | °C/W | Note 2: natural convection, TA = 25°C, JEDEC 51-3 test board | 3 | ||
| Package Thermal Resistance Junction-to-Case SO8E | θJC | 10 | °C/W | 3 |
CAD (KiCad official)
- Symbol:
SY59119A1FCC - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOP-8-EP (KiCad packages3D, STEP)
- 3D model files:
sy59119a1fcc-etched.step/sy59119a1fcc-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sy59119a1fcc.step/sy59119a1fcc.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Silergy Corp datasheet (9 pp, sha256
868552747361fd4a, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SY59119A1FCC
**Silergy Corp** · LED Drivers · SOP-8-EP
SY59119A1FCC from Silergy Corp, in a SOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | LX2 | passive | Drain of the bleeding MOS; the absolute maximum rating for LX2 is -0.3 V to 700 V (page 3). |
| 2 | HVCC | power_in | High-voltage power supply pin; the absolute maximum rating for HVCC is -0.3 V to 700 V (page 3). |
| 3 | NC | unconnected | No connect. |
| 4 | LX1 | passive | Drain of the main MOS; the absolute maximum rating for LX1 is -0.3 V to 500 V (page 3). |
| 5 | TFB | passive | Thermal foldback setting pin, set by a resistor from the datasheet TFB table (RTFB); the absolute maximum rating is -0.3 V to 3.6 V (page 3). |
| 6 | ISEN1 | input | Main MOS current sense pin used to set the output current together with ISEN2; the absolute maximum rating is -0.3 V to 3.6 V (page 3). |
| 7 | ISEN2 | input | BLD MOS current sense pin used to adjust the latching current via RISEN2, with a recommended value RISEN2 > 0.7 ohm; the absolute maximum rating is -0.3 V to 3.6 V (page 3). |
| 8 | VCC | power_in | Power supply pin; the absolute maximum rating for VCC is -0.3 V to 22 V (page 3). |
| 9 | GND | power_in | Ground reference pin. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Silergy Corp |
| Package | SOP-8-EP |
| Category | LED Drivers |
| Pins | 9 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN Turn-on Threshold | VVIN_ON | 11 | 12.1 | 13.2 | V | | 4 |
| VIN Turn-off Threshold | VVIN_OFF | 7.8 | 8.8 | 9.8 | V | | 4 |
| Quiescent Current | IQ | 210 | 280 | 350 | µA | | 4 |
| Internal Reference Voltage | VREF | 0.291 | 0.3 | 0.309 | V | | 4 |
| Voltage on LX2, HVCC (absolute maximum) | | -0.3 | | 700 | V | | 3 |
| Voltage on LX1 (absolute maximum) | | -0.3 | | 500 | V | | 3 |
| Voltage on TFB, ISEN1, ISEN2 (absolute maximum) | | -0.3 | | 3.6 | V | | 3 |
| Voltage on VCC (absolute maximum) | | -0.3 | | 22 | V | | 3 |
| Power Dissipation SO8E | | | | 3.3 | W | @ TA = 25°C, SO8E | 3 |
| Junction Temperature Range (absolute maximum) | | -40 | | 150 | °C | | 3 |
| Lead Temperature (soldering) | | | | 260 | °C | Soldering, 10 sec. | 3 |
| Storage Temperature Range | | -65 | | 150 | °C | | 3 |
| Junction Temperature Range (recommended operating) | | -40 | | 150 | °C | | 3 |
| Ambient Temperature Range (recommended operating) | | -40 | | 120 | °C | | 3 |
| Clamped Current of LX1 MOS | ICLP | | 32 | | mA | | 4 |
| BV of LX1 MOS | VBV_LX1 | | 500 | | V | | 4 |
| BV of LX2 MOS | VBV_LX2 | | 700 | | V | | 4 |
| Minimum Thermal Foldback Temperature | TFB1 | | 115 | | °C | | 4 |
| Maximum Thermal Foldback Temperature | TFB2 | | 155 | | °C | | 4 |
| Package Thermal Resistance Junction-to-Ambient SO8E | θJA | | 30 | | °C/W | Note 2: natural convection, TA = 25°C, JEDEC 51-3 test board | 3 |
| Package Thermal Resistance Junction-to-Case SO8E | θJC | | 10 | | °C/W | | 3 |
## CAD (KiCad official)
- Symbol: `SY59119A1FCC`
- Footprint: `Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm`
- 3D model: SOP-8-EP (KiCad packages3D, STEP)
- 3D model files: `sy59119a1fcc-etched.step` / `sy59119a1fcc-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sy59119a1fcc.step` / `sy59119a1fcc.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Silergy Corp datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590917253531443200) (9 pp, sha256 `868552747361fd4a`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sy59119a1fcc-datasheet.pdf)