component

STS10DN3LH5

Public Made by Adom

by adom

STMicroelectronics MOSFETs, SO-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs sts10dn3lh5: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
viewers sts10dn3lh5: viewers · Ray 1mo ago
package.json Publish 0.1.0 · Ray 1mo ago
page.json sts10dn3lh5: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 1mo ago
README.md sts10dn3lh5: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 1mo ago
sts10dn3lh5-etched.fit.json sts10dn3lh5: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
sts10dn3lh5-etched.glb sts10dn3lh5: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
sts10dn3lh5-etched.step sts10dn3lh5: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
sts10dn3lh5.glb Publish 0.1.0 · Ray 1mo ago
sts10dn3lh5.kicad_mod Publish 0.1.0 · Ray 1mo ago
sts10dn3lh5.kicad_sym Publish 0.1.0 · Ray 1mo ago
sts10dn3lh5.lbr Publish 0.1.0 · Ray 1mo ago
sts10dn3lh5.step Publish 0.1.0 · Ray 1mo ago

STS10DN3LH5

STMicroelectronics · MOSFETs · SO-8

STS10DN3LH5 from STMicroelectronics, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S1 passive Source of MOSFET 1. Return terminal for MOSFET 1 channel current (ID up to 10 A continuous at TC = 25 °C). Also anode of MOSFET 1 intrinsic body diode (VSD typ 1.1 V at ISD = 5 A).
2 G1 input Gate of MOSFET 1. Control input; VGS(th) typ 1 V (at ID = 250 µA), VGS absolute max ±22 V. Total gate charge Qg typ 4.6 nC at VGS = 5 V, VDD = 15 V, ID = 10 A.
3 S2 passive Source of MOSFET 2. Return terminal for MOSFET 2 channel current (ID up to 10 A continuous at TC = 25 °C). Also anode of MOSFET 2 intrinsic body diode.
4 G2 input Gate of MOSFET 2. Control input; VGS(th) typ 1 V, VGS absolute max ±22 V. Independent from G1 (dual device with two separate control gates).
5 D2 passive Drain of MOSFET 2 (pin 5 of the D2 pair). Tied internally to pin 6 to double the drain bond-wire/lead current capacity. VDS max 30 V, ID up to 10 A continuous at TC = 25 °C.
6 D2 passive Drain of MOSFET 2 (pin 6 of the D2 pair). Internally common with pin 5. Also cathode of MOSFET 2 intrinsic body diode.
7 D1 passive Drain of MOSFET 1 (pin 7 of the D1 pair). Internally common with pin 8. VDS max 30 V, ID up to 10 A continuous at TC = 25 °C.
8 D1 passive Drain of MOSFET 1 (pin 8 of the D1 pair). Tied internally to pin 7 to double the drain lead current capacity. Also cathode of MOSFET 1 intrinsic body diode.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package SO-8
Category Transistors/Thyristors
Pins 8

Ordering variants

Same part, different packaging or reel option.

  • STS10DN3LH5

CAD (KiCad official)

  • Symbol: STS10DN3LH5
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)
  • 3D model files: sts10dn3lh5-etched.step / sts10dn3lh5-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sts10dn3lh5.step / sts10dn3lh5.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (None pp, sha256 3ef6beac225d39d4, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF